Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 1/11/2022
Public

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2.7.10.1. Clock Gating

An alternate method to avoid spurious writes of initialized content memories is to implement clock gating circuitry in the PR static region, and feed the clock gating circuitry to the PR region in which the initialized memories are implemented.
Global Clock Control Block

Implement the gating circuitry in the static region, and feed it to the PR region in which the initialized memories are being implemented. Clock gating is logically equivalent to using clock enable on the memories. This method provides the following benefits:

  • Uses the enable port of the global clock buffers to disable the clock before starting the partial reconfiguration operation. Also enables the clock on PR completion.
  • Ensures that the clock does not switch during reconfiguration, and requires no additional logic to avoid spurious writes.

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