Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 1/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.4.3. Partial Reconfiguration External Controller Intel FPGA IP Timing Specifications

Timing Specifications: Partial Reconfiguration External Controller Intel FPGA IP illustrates a successful PR operation with the Partial Reconfiguration External Controller Intel FPGA IP. The PR operation initiates upon assertion of the pr_request signal. The avst_ready output signal indicates whether the SDM is ready to accept data from an external host.

Figure 64. Timing Specifications: Partial Reconfiguration External Controller Intel FPGA IP

Did you find the information on this page useful?

Characters remaining:

Feedback Message