Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 1/11/2022
Public

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3.5. Partial Reconfiguration Region Controller Intel® FPGA IP

The Partial Reconfiguration Region Controller Intel® FPGA IP provides a standard interface through the Freeze Control block that controls handshaking with the PR region. The PR handshake ensures that PR region transactions complete before freeze of the interface.
Table 36.  PR Region Controller Sections
IP Component Description
Freeze Control and Status Register Freeze status register that generates the freeze output signal.
Freeze Control Block Performs PR handshaking and resets the PR region.
Conduit Splitter Connects the controller's freeze signal to one or more Freeze Bridge components. Receives the freeze signal from the Freeze Control Block, and assigns the freeze input signal to one or more freeze output signals.
Conduit Merger Connects the illegal_request signal from one or more Freeze Bridge components to the PR Region Controller.

The illegal_request is a single-bit output signal from the Freeze Bridge. Conduit Merger concatenates the single-bit signal from multiple Freeze Bridges into a multi-bit bus. The Conduit Merger then connects the bus to the Freeze Control Block.

Figure 65. Partial Reconfiguration Region Controller IP Core

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