Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

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ID 683834
Date 1/11/2022
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2.10. Partial Reconfiguration Design Simulation

Simulation verifies the behavior of your design before device programming. The Intel® Quartus® Prime Pro Edition software supports simulating the delivery of a partial reconfiguration bitstream to the PR region. This simulation allows you to observe the resulting change and the intermediate effect in a reconfigurable partition.

The Intel® Quartus® Prime Pro Edition software supports simulation of PR persona transitions through the use of simulation multiplexers. You use the simulation multiplexers to change which persona drives logic inside the PR region during simulation. This simulation allows you to observe the resulting change and the intermediate effect in a reconfigurable partition.

Similar to non-PR design simulations, preparing for a PR simulation involves setting up your simulator working environment, compiling simulation model libraries, and running your simulation.

The Intel® Quartus® Prime software provides simulation components to help simulate a PR design, and can generate the gate-level PR simulation models for each persona. Use either the behavioral RTL or the gate-level PR simulation model for simulation of the PR personas. The gate-level PR simulation model allows for accurate simulation of registers in your design and reset sequence verification. These technology-mapped registers do not assume initial conditions.

You can use the PR mode of the EDA netlist writer to generate the gate level netlist of a PR region. Refer to the "EDA Netlist Writer and Gate Level-Netlists" section of the Intel® Quartus® Prime Pro Edition User Guide: Third Party Simulation.

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