Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 1/11/2022
Public

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3.8.5. Generating the PR Persona Simulation Model

Use the Intel® Quartus® Prime EDA Netlist Writer to create the simulation model for a PR persona. The simulation model represents the post-synthesis, gate-level netlist for the persona.

When using the PR simulation model for the persona, the netlist includes a new altera_sim_pr_activate top-level signal for the model. You can asynchronously drive this signal to load all registers in the model with X. This feature allows you to verify the reset sequence of the new persona on PR event completion. Verify the reset sequence through inspection, using SystemVerilog assertions, or using other checkers.

By default, the PR simulation model asynchronously loads X into the register’s storage element on pr_activate signal assertion. You can parameterize this behavior on a per register basis, or on a simulation-wide default basis. The simulation model supports four built-in modes:

  • load X
  • load 1
  • load 0
  • load rand

Specify these modes using the SystemVerilog classes:

  • dffeas_pr_load_x
  • dffeas_load_1
  • dffeas_load_0
  • dffeas_load_rand

Optionally, you can create your own PR activation class, where your class must define the pr_load variable to specify the PR activation value.

Follow these steps to generate the simulation model for a PR design:

  1. Open the base revision of a PR project in Intel® Quartus® Prime Pro Edition, and then click Processing > Start > Start Analysis & Synthesis. Alternatively, run this command-line equivalent:
    quartus_syn <project name> -c <base revision name>
  2. After synthesis is complete, click Project > Export Design Partition, and then select the root partition for the Partition name, and select synthesized for the Snapshot. Click OK. Alternatively, run this command-line equivalent:
    quartus_cdb <project name> -c <base revision name> \
         "--export_block root_partition --snapshot synthesized \
         --file <static qdb name>
  3. Click Project > Revisions and switch the current revision to that of the persona you want to export.
  4. Click Processing > Start > Start Analysis & Synthesis. Alternatively, run this command-line equivalent:
    quartus_syn <project name> -c <persona revision name>
  5. After synthesis of the persona revision completes, execute the following at the command line to generate the PR simulation model:
    quartus_eda <project name> –c <persona revision name> "--pr --simulation \
         --tool=modelsim --format=verilog --partition=<pr partition name> \
         --module=<partition name>=<persona module name>
  6. Repeat steps 3 through 5 for all personas that you want to simulate.

Complete PR Simulation Model Generation Script

quartus_syn <project name> -c <base revision name>
quartus_cdb <project name> -c <base revision name> \
     "--export_block root_partition --snapshot synthesized \
     --file <static qdb name>
quartus_syn <project name> -c <persona revision name>
quartus_eda <project name> –c <persona revision name> \
     "--pr --simulation --tool=modelsim --format=verilog \
     --partition=<pr partition name> --module=<partition name>=\
     <persona module name>

You can use the PR mode of the EDA netlist writer to generate the gate level netlist of a PR region. Refer to the "EDA Netlist Writer and Gate Level-Netlists" section of the Intel® Quartus® Prime Pro Edition User Guide: Third Party Simulation.

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