Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 1/11/2022
Public

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3.6. Avalon® Memory-Mapped Partial Reconfiguration Freeze Bridge IP

The Avalon® Memory-Mapped Partial Reconfiguration Freeze Bridge Intel® FPGA IP freezes a PR region Avalon® memory-mapped interface when the freeze input signal is high. It is recommended that each Avalon® memory-mapped interface to a PR region use an instance of the Freeze Bridge IP.
Figure 71.  Avalon® Memory-Mapped Partial Reconfiguration Freeze Bridge IP
Table 46.  Read and Write Request to PR Region Avalon® Memory-Mapped Agent InterfaceThe Freeze Bridge handles read and write transactions differently for each of the following possible interface configurations. The Freeze Bridge is in the freeze state until the PR region or PR region controller asserts the freeze signal.
Interface Connection Behavior
Read request to Avalon® memory-mapped slave interface in PR region
  1. During the freeze state, any read transaction responds with bogus data <h'DEADBEEF>. The corresponding freeze_illegal_request register bit sets.
  2. During the freeze state, readrequest, writerequest, waitrequest, beginbursttransfer, lock, and debugaccess signals in the PR region interface tie low.
  3. The Avalon® memory-mapped agent response signal constantly returns 2’b10, to indicate an unsuccessful transaction from an endpoint agent.
  4. If you disable Enable Freeze port from PR region, the IP generates no responses.
Write request to slave interface in PR region
  1. The Freeze Bridge ignores any write transactions during the freeze state. The Freeze Bridge pulls the waitrequest, beginbursttransfer, lock and debugaccess signals low. The IP sets the corresponding freeze_illegal_request register bit.
  2. The Avalon® memory-mapped agent response signal updates with 2’b10 to indicate an unsuccessful transaction from an endpoint agent.
  3. If you disable Enable Freeze port from PR region, the IP generates no responses.
Table 47.  Read and Write Request from PR Region Avalon® Memory Mapped Host Interface
Interface Connection Behavior
Read/Write request from Avalon® -MM master interface in PR region (old or new persona)
  1. During the freeze state, the IP ignores the read and write signals from the PR region.
  2. The read and write signals to the static region deassert.
Table 48.   Avalon-MM Partial Reconfiguration Freeze Bridge Signal BehaviorThe table below summarizes the Avalon® interface output signal behavior when the Freeze Bridge is in a frozen state. When not frozen, all signals are just pass-through.
Signal Agent Bridge Host Bridge
write ‘b0 (tie low) ‘b0 (tie low)
read ‘b0 (tie low) ‘b0 (tie low)
address Pass through Pass through
writedata Pass through Pass through
readdata Return <h’DEADBEEF> always Pass through
byteenable Pass through Pass through
burstcount Pass through Pass through
beginbursttransfer ‘b0 (tie low) ‘b0 (tie low)
debugaccess ‘b0 (tie low) ‘b0 (tie low)
readdatavalid Return ‘b1 when there is a request, else ‘b0 Pass through
waitrequest Return ‘b1 when there is a request, else ‘b0 ‘b0 (tie low)
response Return ‘b10 always Pass through
lock ‘b0 (tie low) ‘b0 (tie low)
writeresponsevalid Return ‘b1 when there is a request, else ‘b0 Pass through

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