Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

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ID 683834
Date 1/11/2022
Public

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2.6.4.2. Adding the Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 FPGA IP

The Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 FPGA IP interfaces with the Intel® Arria® 10 or Intel® Cyclone® 10 GX PR control block to manage the bitstream source.

Use this IP core in Intel® Arria® 10 or Intel® Cyclone® 10 GX designs when performing partial reconfiguration with an internal PR host, Nios® II processor, PCI Express* , or Ethernet interface.

During partial reconfiguration, you send a PR bitstream stored outside the FPGA to the PR control block inside the FPGA. This communication enables the control block to update the CRAM bits necessary for reconfiguring the PR region in the FPGA. The PR bitstream contains the instructions (opcodes) and the configuration bits necessary for reconfiguring a specific PR region.

Figure 10.  Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 FPGA IP

Instantiate the IP core from the Intel® Quartus® Prime IP Catalog (Tools > IP Catalog) to automatically connect the IP to the Intel® Arria® 10 or Intel® Cyclone® 10 GX PR control block.

If you create your own custom logic to perform the function of the IP core, manually instantiate the control block to communicate with the FPGA system.

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