Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

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ID 683834
Date 1/11/2022
Public

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3.7.1. Parameters

The Avalon® Streaming Partial Reconfiguration Freeze Bridge IP core supports customization of the following parameters:
Figure 78. Parameter Editor
Table 57.  Parameters
Parameter Values Description
PR region Interface Type Avalon-ST Source/Avalon-ST Sink Specifies the interface type for interfacing the PR region with the freeze bridge.
Enable Freeze port from PR region On/Off Enables the freeze port to freeze all the outputs of each PR region to a known constant value. Freezing prevents the signal receivers in the static region from receiving undefined signals during the partial reconfiguration process.
Select Yes or No to enable or disable interface ports Yes/No Enables or disables specific optional freeze bridge interface ports.
Channel width <1-128> Specifies the width of the channel signal.
Error width <1-256> Specifies the width of the error signal.
Data bits per symbol <1-512> Specifies the number of bits per symbol.
Symbols per beat <1-512> Specifies the number of symbols that transfer on every valid clock cycle.
Error descriptors <text> Specifies one or more strings to describe the error condition for each bit of the error port on the sink interface connected to the source interface. Click the plus or minus buttons to add or remove descriptors.
Max channel number <0-255> Specifies the maximum number of output channels.
Ready latency <0-8> Specifies what ready latency to expect from the source interface connected to the sink interface. The ready latency is the number of cycles from the time ready asserts until valid data is driven.

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