Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 1/11/2022
Public

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3.2. Partial Reconfiguration Controller Intel FPGA IP

The Partial Reconfiguration Controller Intel® FPGA IP provides partial reconfiguration functionality for Intel® Stratix® 10 and Intel® Agilex™ designs. The IP core provides a standard interface to the FPGA secure device manager (SDM), and has a maximum clock frequency of 200 MHz.
Figure 38.  Intel® Stratix® 10 and Intel® Agilex™ Partial Reconfiguration Controller ( Avalon® Streaming Interface)
4
Note: If an error occurs during PR operation for an Intel® Stratix® 10 or Intel® Agilex™ design using SEU detection, the PR region is frozen, becomes non-functional, and SEU detection is disabled for all sectors within the PR region and certain sectors adjacent to PR region. To resolve this error and restore SEU detection on affected areas, perform a full chip configuration.
4 Avalon memory mapped interface variant also available.

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