Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 1/11/2022
Public

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3.5.3. Ports

The Partial Reconfiguration Region Controller IP has the following ports.
Table 43.  Freeze CSR Block PortsThese ports are available when Enable Avalon® Memory-Mapped CSR Register is On.
Port Width Direction Description
clock_clk 1 Input IP core input clock.
Reset
reset_reset 1 Input Synchronous reset.
avl_csr_addr 2 Input Avalon® memory-mapped address bus. The address bus is in word addressing.
avl_csr_read 1 Input Avalon® memory-mapped read control to CSR block.
avl_csr_write 1 Input Avalon® memory-mapped write control to CSR.
avl_csr_writedata 32 Input Avalon® memory-mapped write data bus to CSR.
avl_csr_readdata 32 Output Avalon® memory-mapped read data bus from CSR.
interrupt_sender_irq 1 output Trigger by illegal read or illegal write.
Table 44.  Freeze Control Block Ports
Port Width Direction Description

pr_handshake_stop_req

1 Output An assertion on this output requests that the PR persona stop executing.

pr_handshake_stop_ack

1 Input A value of 1 on this input acknowledges that the executing PR persona stops executing and a new persona can replace it.

pr_handshake_start_req

1 Output An assertion on this output requests that the new PR persona starts executing.

pr_handshake_start_ack

1 Input A value of 1 on this input acknowledges that the new PR persona starts executing and can stop executing on a pr_handshake_stop_req.
conduit_control_freeze_req 1 Input

Write 1 on this bit to start freezing the PR region interfaces.

conduit_control_unfreeze_req 1 Input Write 1 on this bit to stop freezing the PR region interfaces.
conduit_control_freeze_status 1 Output High on this bit indicates that the PR region is successfully goes into freezing state.
conduit_control_reset 1 Input Write 1 on this bit to reset the PR region.
conduit_control_unfreeze_status 1 Output High on this bit indicates that the PR region successfully leaves freezing state.
conduit_control_illegal_req n Output High on this bit indicates illegal data transactions occurring through a Freeze Bridge IP when freeze is active.
Table 45.  Conduit Splitter and Merger Interface Ports
Signal Width Direction Description
bridge_freeze0_freeze 1 Output This output connects to the freeze input signal of a freeze bridge IP or to control other freeze logic. (Multiple interfaces generate according to the number of freeze interfaces)
bridge_freeze0_illegal_request 1 Input This input connects to the illegal_request output signal from an instance of the Freeze Bridge IP.
Figure 69.  Partial Reconfiguration Region Controller Interface Ports (Control and Status Register Block Enabled)
Figure 70.  Partial Reconfiguration Region Controller Interface Ports (Control and Status Register Block Disabled)

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