Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

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ID 683834
Date 1/11/2022
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2.3. Partial Reconfiguration Process Sequence

Your partial reconfiguration design must initiate the PR operation and deliver the configuration file to the PR control block ( Intel® Arria® 10 and Intel® Cyclone® 10 GX designs) or SDM ( Intel® Agilex™ and Intel® Stratix® 10 designs). Before partial reconfiguration, you must ensure that the FPGA device is in user mode, and in a functional state. The following steps describe the partial reconfiguration sequence:
  1. Send the stop_req signal to the PR region from the sequential PR control logic to prepare for the PR operation. Upon receiving this signal, the PR regions complete any pending transactions and stop accepting new transactions.
  2. Wait for the stop_ack signal to indicate that the PR region is ready for partial reconfiguration.
  3. Use PR control logic to freeze all necessary outputs of the PR regions. Additionally, drive the clock enable for any initialized RAMs to a disabled state.
  4. Send the PR bitstream to the PR control block ( Intel® Arria® 10 and Intel® Cyclone® 10 GX designs) or SDM ( Intel® Stratix® 10 and Intel® Agilex™ designs) to initiate the PR process for the PR region. When using any of the Partial Reconfiguration Controller Intel® FPGA IP, the Avalon® memory-mapped or Avalon® streaming interface on the IP core provides this functionality. When directly instantiating the PR control block for Intel® Arria® 10 designs, refer to PR Control Block Signal Timing Diagrams
  5. On successful completion of the PR operation, reset the PR region.
  6. Signal the start of PR operation by asserting the start_req signal, and deasserting the freeze signal.
  7. Wait for the start_ack signal to indicate that the PR region is ready for operation.
  8. Resume operation of the FPGA with the newly reconfigured PR region.
Figure 2. PR Process Sequence Timing Diagram

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