Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 1/11/2022
Public

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Document Table of Contents

3.10. Partial Reconfiguration Solutions IP User Guide Revision History

Document Version Intel® Quartus® Prime Version Changes
2022.01.11 21.4
  • Revised Partial Reconfiguration Controller Intel FPGA IP section to reflect the new error recovery mechanism that flushes out any remaining corrupted PR bitstream that might be left in user logic pipeline after sending a corrupted bitstream.
  • Revised Partial Reconfiguration Controller Intel FPGA IP Parameters topic for new Enable Protocol Checker and Enable SDM FW Error Reporting parameters that report additional error handshake status and response for detailed error analysis in PR Controller FPGA IP for internal host and debug SDM JTAG command for external host.
  • Added new PR Error Recovery topic.
  • Added new PR Error Recovery Timing Specifications topic.
  • Added new Secure Device Manager Firmware Error Reporting topic.
  • Added new SDM Firmware Error Reporting Timing Specifications topic.
  • Added new Partial Reconfiguration External Controller Intel FPGA IP Timing Specifications topic.
  • Added new Secure Device Manager Partial Reconfiguration Simulation Model section.
  • Corrected typo in Agent Interface topic.
2021.10.04 21.3
  • Updated Partial Reconfiguration External Configuration Controller Intel® FPGA IP Ports topic status bit information.
  • Updated Partial Reconfiguration Controller Intel® FPGA IP Ports topic status bit information.
  • Updated non-inclusive terms with "host" and "agent" for Avalon Memory Mapped interface references throughout.
2021.08.02 21.2
  • Updated Partial Reconfiguration Controller Intel® FPGA IP topic SEU note.
  • Revised Register States and Programming Model figure to correct sequence.
2020.09.28 20.3
  • Replaced references to Avalon-MM and Avalon-ST with Avalon memory-mapped and Avalon streaming for legal compliance.
2020.08.07 20.2
  • Corrected signal name typos in "Interface Ports" topic for Avalon-MM Partial Reconfiguration Freeze Bridge Intel® FPGA IP.
2019.12.16 19.4.0
  • Added "Error Detection CRC Requirements" topic.
2019.09.30 19.3.0
  • Updated the name of "Intel Stratix 10 Partial Reconfiguration Controller FPGA IP" to "Partial Reconfiguration Controller Intel FPGA IP" to encompass support for Intel® Agilex™ devices.
  • Added note about connection of dummy_clk in "PR Control Block and CRC Block VHDL Module."
  • Added note to "PR Bitstream Compression and Encryption" topic about support for enhanced decompression.
2019.06.07 19.1.0
  • Added note and reference to Intel® Stratix® 10 Configuration User Guide.
2019.04.22 19.1.0
  • Indicated support for POF generation support for Intel Cyclone GX devices.
2019.01.04 18.1.0
  • Clarified statement about configuration width in "Control Block Signals" topic.
2018.12.07 18.1.0
  • Corrected typographical error in "Partial Reconfiguration IP Cores" table.
  • Corrected typographical error in " Avalon® -MM Slave to PR Region Master Interface Ports" table.
2018.09.24 18.1.0
  • Updated specification for Partial Reconfiguration Controller Intel® Stratix® 10 FPGA IP from 250 MHz to 200 MHz.
  • Stated PR compilation flow support for Intel® Cyclone® 10 GX devices.
  • Updated Partial Reconfiguration Controller Intel® Arria® 10 FPGA IP name to Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 FPGA IP.
2018.06.27 18.0.0 Updated freeze_status signal description in Registers: Partial Reconfiguration Region Controller .
2018.06.18 18.0.0
  • Corrected syntax error in Generating the PR Persona Simulation Model.
2018.05.07 18.0.0
  • Added description of new Partial Reconfiguration External Configuration Controller Intel® Stratix® 10 FPGA IP.
  • Updated names of Partial Reconfiguration Controller Intel® Arria® 10 FPGA IP and Partial Reconfiguration Controller Intel® Stratix® 10 FPGA IP.
  • Enhanced explanation of Auto-instantiate CRC block Partial Reconfiguration Controller Intel® Arria® 10 parameter.
  • Added as chapter in new Partial Reconfiguration User Guide.
  • Added note about recovery after PR error when using SEU detection in Intel® Stratix® 10 designs.
2017.11.06 17.1.0
  • Added support for Intel® Stratix® 10 Partial Reconfiguration Controller IP core.
  • Updated for latest Intel® product naming conventions.
2017.05.08 17.0.0 Initial public release.

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