Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

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ID 683834
Date 1/11/2022
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2.2. Partial Reconfiguration Terminology

This document refers to the following terms to explain partial reconfiguration:

Table 1.  Partial Reconfiguration Terminology
Term Description

Floorplan

The layout of physical resources on the device. Creating a design floorplan, or floorplanning, is the process of mapping the logical design hierarchy to physical regions in the device. PR requires floorplanning.

Hierarchical Partial Reconfiguration Partial reconfiguration that includes multiple parent and child design partitions, or nesting of partitions in the same design.

PR control block

A dedicated block in Intel® Arria® 10 and Intel® Cyclone® 10 GX FPGAs. The PR control block processes the PR requests, handshake protocols, and verifies the cyclic redundancy check (CRC).

PR host

The system for coordinating PR. The PR host communicates with the PR control block ( Intel® Arria® 10 and Intel® Cyclone® 10 GX designs) or Secure Device Manager ( Intel® Stratix® 10 and Intel® Agilex™ designs). Implement the PR host within the FPGA (internal PR host) or in a chip or microprocessor.

PR partition

Design partition that you designate as Reconfigurable. A PR project can contain one or more PR partitions.

PR Solutions Intel® FPGA IP

Suite of Intel® FPGA IP that simplify implementation of PR handshaking and freeze logic, as Partial Reconfiguration Solutions IP User Guide describes.

PR region

A physical portion of an FPGA device that you designate for partial reconfiguration. You define a PR region in the base configuration design. A device can contain more than one PR region. A PR region must be core-only, containing only core resources like LABs, RAM blocks, and DSP blocks. The PR region bitstream configures this region.

PR persona

A specific PR partition implementation in a PR region. A PR region can contain multiple personas. Static regions contain only one persona.

Revision

A collection of settings and constraints for one version of your project. An Intel® Quartus® Prime Settings File (.qsf) preserves each revision of your project. Your Intel® Quartus® Prime project can contain several revisions. Revisions allow you to organize several versions of your design within a single project.

Secure Device Manager (SDM) A triple-redundant processor-based block in Intel® Agilex™ and Intel® Stratix® 10 devices that performs authentication, decryption, and decompression on the configuration data the block receives, before sending the data over to the configurable nodes through the configuration network.

Snapshot

The output of a Compiler stage. You can export the synthesis or final compilation results snapshot.

Static region

All areas not occupied by PR regions in your project. You associate the static region with the top-level partition of the design. The static region contains both the core and periphery locations of the device. The static region bitstream configures this region.

Static update partial reconfiguration A static region that you can change, without requiring the recompilation of all personas. This technique is useful for a portion of a design that you may possibly want to change for risk mitigation, but that never requires runtime reconfiguration.

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