Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

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ID 683834
Date 1/11/2022
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2.7.2. PR Design Timing Closure Best Practices

The use of partition boundary ports for PR regions can make timing closure more challenging because the Compiler cannot optimize the logic across a partition boundary. The use of Logic Lock regions can also limit placement and routing flexibility. You must register all PR region boundary ports. Even when taking these steps, you may still find timing criticalities.

Each persona of a PR region can have different bits or input and output buses in use. Therefore, it is important to preserve the registers that do not have fan-out in a given persona, or that are driven by constants. You must ensure that the Compiler does not optimize away such registers during the compilation of a persona.

If the base compile does not use some bits of a bus, and the Compiler removes the corresponding registers for those bits, the logic may be untimed, resulting in unfavorable placement and routing. If you use those unregistered paths in other persona logic, you can have difficulty meeting timing on those paths. Preserving the unused port registers in the base compile ensures that the paths are timed in the base compile, and eases timing closure during persona compiles.

Follow these guidelines for effective register preservation in PR designs:

  • Only the registers within PR regions require preservation.
  • Only the PR base compilation requires register preservation.
  • In a persona compile, the Compiler can safely remove fan-out free and constant-driven registers.
  • For hierarchical PR compilations, only the base compile of the hierarchy requires register preservation.
  • Preserve fan-out free nodes for input registers.
  • Preserve constant-driven nodes for output registers.
  • Only assign the attributes for the PR base compile. Remove the attributes for the persona compile (for example, via parameter or generic).
  • You can set top-level parameters in the .qsf, which in turn pass down to lower hierarchies.

Use any of the following synthesis attributes to preserve registers:

  • To preserve constant-driven or fan-out free registers, use the noprune attribute. noprune also disables all physical optimizations:
    Verilog: (* noprune *) reg reg1;
    VHDL: signal reg1: std_logic; 
          attribute noprune: boolean; 
          attribute noprune of reg1: signal is true;
  • To preserve fan-out free registers while allowing retiming on bits that have fan-outs, assign PRESERVE_FANOUT_FREE_NODE ON as altera_attribute:
    Verilog: (* altera_attribute = "-name PRESERVE_FANOUT_FREE_NODE ON" *) \
         reg reg1;
    VHDL: signal reg1: stdlogic; 
          attribute altera_attribute : string; 
          attribute altera_attribute of reg1: signal is "-name \
         PRESERVE_FANOUT_FREE_NODE ON";
  • Alternatively, use the dummy attribute with the PRESERVE_FANOUT_FREE_NODE ON assignment in the .qsf:
    Verilog: (* dummy *) reg reg1;
    VHDL: signal reg1: std_logic; 
          attribute dummy: boolean; 
          attribute dummy of reg1: signal is true;

    .qsf Assignment:

    set_instance_assignment -name PRESERVE_FANOUT_FREE_NODE ON \
        -to <hierarchical path to reg1>
  • To preserve constant-driven registers while allowing retiming on bits that have drivers, use the preserve_syn_only attribute:
    Verilog: (* preserve_syn_only *) reg reg1;
    VHDL: signal reg1: std_logic; 
          attribute preserve_syn_only : boolean; 
          attribute preserve_syn_only of reg1: signal is true;

The following example shows how to assign attributes in PR base compile using a parameter in System Verilog and in VHDL. The example contains a parameter called base_compile, which is set to true for the PR base compile only.

System Verilog:
localparam ON_OFF_STRING = base_compile ? "ON": "OFF";
(* altera_attribute = {"-name PRESERVE_FANOUT_FREE_NODE ", ON_OFF_STRING} *)
logic [WIDTH-1:0] pr_input_register;
(* altera_attribute = {"-name PRESERVE_REGISTER_SYN_ONLY ", ON_OFF_STRING} *)
logic [WIDTH-1:0] pr_output_regsiter;

VHDL:
attribute altera_attribute : string;
type attributeStr_type is array(boolean) of string(1 to 35);
constant attributeStr : attributeStr_type := (true => "-name PRESERVE_FANOUT_FREE_NODE ON \
     ", false => "-name PRESERVE_FANOUT_FREE_NODE OFF");
attribute altera_attribute of  <PR input registers> : signal is attributeStr(base_compile);
attribute preserve_syn_only : boolean;
attribute preserve_syn_only of  <PR output registers> : signal is base_compile;

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