Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

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ID 683834
Date 1/11/2022
Public

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2.6.9. Step 9: Program the FPGA Device

The Intel® Quartus® Prime Assembler generates the PR bitstreams for your design personas. For Intel® Arria® 10 and Intel® Cyclone® 10 GX designs, you send the bitstreams to the PR control block. For Intel® Stratix® 10 and Intel® Agilex™ designs, you send the PR bitstreams to the SDM. You must compile the PR project, including the base revision, and at least one implementation revision, before generating the PR bitstreams.

For Intel® Stratix® 10 and Intel® Agilex™ designs, the Assembler generates a configuration .rbf automatically at the end of compilation. For Intel® Arria® 10 and Intel® Cyclone® 10 GX designs, you can add the GENERATE_PR_RBF_FILE assignment to the .qsf or use the Convert Programming Files dialog box to convert the Partial-Masked SRAM Object Files (.pmsf) to an .rbf file, as Generating PR Bitstream Files describes.

Programming File Generation
Table 4.  PR Programming Files
Programming File Description
<rev>.<pr_region>.pmsf Contains the partial-mask bits for the PR region. The .pmsf file contains all the information for creating PR bitstreams.
Note: The default file name corresponds to the partition name.
<rev>.<static_region>.msf Contains the mask bits for the static region.
<rev>.sof Contains configuration information for the entire device.

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