Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

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ID 683834
Date 1/11/2022
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3.2.5. PR Error Recovery

The Partial Reconfiguration Controller Intel® FPGA IP supports error recovery during partial reconfiguration.

When PR_ERROR triggers, the PR Controller IP initiates the error recovery mechanism by de-asserting the avst_sink_ready signal to flush out any remaining corrupted PR bitstream that remains in the Avalon streaming pipeline.

Note: You must ensure that the remaining corrupted PR bitstream is fully flushed from the Avalon streaming pipeline before initiating another PR operation, or before performing a PR controller IP reset.

For PR Controller IP designs that have an Avalon memory-mapped interface, when PR_ERROR is triggered, continue to write (by asserting both avmm_slave_write and avmm_slave_writedata) until the PR bitstream in the Avalon memory-mapped host depletes.

To prevent inadvertent flushing of the new bitstream, do not provide a new, uncorrupted PR bitstream to the PR Controller IP until flushing is complete. Once flushing is complete, you can send a new, uncorrupted PR bitstream to the PR controller IP when pr_start is asserted and after the reset is de-asserted.

Note:

Once the PR process initiates, you cannot alter nor replace the PR bitstream provided in the Avalon streaming pipeline. For example, if the PR Controller IP reflects a status of configuration is busy (3’b001), you must re-initiate PR with the PR bitstream that is already present, without replacing the bitstream. The existing PR bitstream must undergo the whole PR process until the PR operation completes with status of either success (3’b011) or fail (PR_ERROR is triggered: 3’b100, or incompatible bitstream error: 3’b110) with the error recovery mechanism to clear the Avalon streaming pipeline.

After one of the statuses occurs, you can send the PR bitstream to the PR Controller IP when initiating another PR operation, or after performing a PR Controller IP reset.

This PR error recovery feature is available only for the Partial Reconfiguration Controller Intel® FPGA IP, which controls Avalon streaming and Avalon memory-mapped paths where the data comes in.

The Partial Reconfiguration Controller Intel® FPGA IP only acts as a block that reports the handshaking of the external user host and the SDM of the FPGA. There is no interaction between the streaming path and the IP. You connect directly to the Avalon streaming pins in the SDM I/O. These SDM I/O pins are exactly the same as the Avalon Streaming pins that you use for full device configuration. The PR IP cannot control the SDM I/O pins.

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