Nios II Classic Processor Reference Guide

ID 683620
Date 10/28/2016
Public
Document Table of Contents

2.3.3. Floating-Point Instructions

The Nios II architecture supports single precision floating-point instructions with two components:
  • Floating Point Hardware 2—This component supports floating-point instructions as specified by the IEEE Std 754-2008 but with simplified, non-standard rounding modes. The basic set of floating-point custom instructions includes single precision floating-point addition, subtraction, multiplication, division, square root, integer to float conversion, float to integer conversion, minimum, maximum, negate, absolute, and comparisons.
  • Floating Point Hardware—This component supports floating-point instructions as specified by the IEEE Std 754-1985. The basic set of floating-point custom instructions includes single precision floating-point addition, subtraction, and multiplication. Floating-point division is available as an extension to the basic instruction set.

These floating-point instructions are implemented as custom instructions. The Hardware Conformance table below lists a detailed description of the conformance to the IEEE standards.

Table 3.  Hardware Conformance with IEEE 754-1985 and IEEE 754-2008 Floating-Point Standard
Feature Floating-Point Hardware Implementation with IEEE 754-1985 Floating-Point Hardware 2 Implementation with IEEE 754-2008
Operations Addition/subtraction Implemented Implemented
Multiplication Implemented Implemented
Division Optional Implemented
Square root Not implemented, this operation is implemented in software. Implemented
Integer to float/float to integer Not implemented, this operation is implemented in software. Implemented
Minimum/maximum Not implemented, this operation is implemented in software. Implemented
Negate/absolute Not implemented, this operation is implemented in software. Implemented
Comparisons Not implemented, this operation is implemented in software. Implemented
Precision Single Implemented Implemented
Double Not implemented. Double precision operations are implemented in software. Not implemented. Double precision operations are implemented in software.
Exception conditions Invalid operation Result is Not a Number (NaN) Result is Not a Number (NaN)
Division by zero Result is ±infinity Result is ±infinity
Overflow Result is ±infinity Result is ±infinity
Inexact Result is a normal number Result is a normal number
Underflow Result is ±0 Result is ±0
Rounding Modes Round to nearest Implemented Implemented (roundTiesToAway mode)
Round toward zero Not implemented Implemented (truncation mode)
Round toward +infinity Not implemented Not implemented
Round toward –infinity Not implemented Not implemented
NaN Quiet Implemented No distinction is made between signaling and quiet NaNs as input operands. A result that produces a NaN may produce either a signaling or quiet NaN.
Signaling Not implemented
Subnormal (denormalized) numbers   Subnormal operands are treated as zero. The floating-point custom instructions do not generate subnormal numbers.
  • The comparison, minimum, maximum, negate, and absolute operations support subnormal numbers.
  • The add, subtract, multiply, divide, square root, and float to integer operations do NOT support subnormal numbers. Subnormal operands are treated as signed zero. The floating-point custom instructions do not generate subnormal numbers.1
  • The integer to float operation cannot create subnormal numbers.
Software exceptions   Not implemented. IEEE 754-1985 exception conditions are detected and handled as described elsewhere in this table. Not implemented. IEEE 754-2008 exception conditions are detected and handled as described elsewhere in this table.1
Status flags   Not implemented. IEEE 754-1985 exception conditions are detected and handled as described elsewhere in this table. Not implemented. IEEE 754-2008 exception conditions are detected and handled as described elsewhere in this table.1
Note: The Floating Point Hardware 2 component also supports faithful rounding, which is not an IEEE 754-defined rounding mode. Faithful rounding rounds results to either the upper or lower nearest single-precision numbers. Therefore, the result produced is one of two possible values and the choice between the two is not defined. The maximum error of faithful rounding is 1 unit in the last place (ulp). Errors may not be evenly distributed.
1 This operation is not fully compliant with IEEE 754-2008.

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