Nios II Classic Processor Reference Guide

ID 683620
Date 10/28/2016
Document Table of Contents

6.3.1. Nios II/f Core

Table 83.  Nios II/f Core Revisions
Version Release Date Notes
13.1 November 2013
  • Added ECC support for internal RAM blocks (instruction cache, MMU TLB, and register file)
  • Added support for enhanced floating-point custom instructions
11.0 May 2011 No changes.
10.1 December 2010 No changes.
10.0 July 2010 No changes.
9.1 November 2009
  • Added optional external interrupt controller interface.
  • Added optional shadow register sets.
9.0 March 2009 No changes.
8.1 November 2008 No changes.
8.0 May 2008
  • Implemented the optional MMU.
  • Implemented the optional MPU.
  • Implemented advanced exception checking.
  • Implemented the initda instruction.
7.2 October 2007 Implemented the jmpi instruction.
7.1 May 2007 No changes.
7.0 March 2007 No changes.
6.1 November 2006 No changes.
6.0 May 2006 Cycle count for flushi and initi instructions changes from 1 to 4 cycles.
5.1 SP1 January 2006 Bug Fix:

Back-to-back store instructions can cause memory corruption to the stored data. If the first store is not to the last word of a cache line and the second store is to the last word of the line, memory corruption occurs.

5.1 October 2005 No changes.
5.0 May 2005
  • Added optional tightly-coupled memory ports. Designers can add zero to four tightly-coupled instruction master ports, and zero to four tightly-coupled data master ports.
  • Made the data cache line size configurable. Designers can configure the data cache with the following line sizes: 4, 16, or 32 bytes. Previously, the data cache line size was fixed at 4 bytes.
  • Made instruction and data caches optional (previously, cache memories were always present). If the instruction cache is not present, the Nios II core does not have an instruction master port, and must use a tightly-coupled instruction memory.
  • Support for HardCopy devices (previous versions required a workaround to support HardCopy devices).
1.1 December 2004
  • Added user-configurable options affecting multiply and shift operations. Now designers can choose one of three options:

    (1) Use embedded multiplier resources available in the target device family (previously available).

    (2) Use logic elements to implement multiply and shift hardware (new option).

    (3) Omit multiply hardware. Shift operations take one cycle per bit shifted; multiply operations are emulated in software (new option).

  • Added cpuid control register.
  • Bug Fix:

    Interrupts that were disabled by wrctl ienable remained enabled for one clock cycle following the wrctl instruction. Now the instruction following such a wrctl cannot be interrupted.

1.01 September 2004
  • Bug Fixes:

    (1) When a store to memory is followed immediately in the pipeline by a load from the same memory location, and the memory location is held in the data cache, the load may return invalid data. This situation can occur in C code compiled with optimization off (-O0).

    (2) The SOPC Builder top-level system module included an extra, unnecessary output port for systems with very small address spaces.

1.0 May 2004 Initial release of the Nios II/f core.