Nios II Classic Processor Reference Guide

ID 683620
Date 10/28/2016
Public
Document Table of Contents

3.7.9.4. Exceptions and Processor Status

The Nios® II Processor Status After Taking Exception Table lists all changes to the Nios® II processor state as a result of nonbreak exception processing actions performed by hardware. For systems with an MMU, status.EH indicates whether or not exception processing is already in progress. When status.EH = 1, exception processing is already in progress and the states of the exception registers are preserved to retain the original exception states.
Table 43.   Nios® II Processor Status After Taking Exception
Processor Status Register or Field System Status Before Taking Exception
External Interrupt Asserted 14 Internal Interrupt Asserted or Noninterrupt Exception
status.EH==1 29 status.EH==0 status.EH==1 status.EH==0
TLB Miss 31 No TLB Miss
RRS==0 30 RRS!=0 RRS==0 RRS!=0 TLB Permission Violation 31 No TLB Permission Violation
pteaddr.VPN 15 No change VPN 16 No change
status.PRS 30 No change status.CRS 30  32 No change
pc RHA General exception vector 17 Fast TLB exception vector 18 General exception vector30
sstatus  19 33 No change status  32 20 No change
estatus 33 No change status 32 No change status 32
ea No change return address 21 No change return address
tlbmisc.D 29 No change 22
tlbmisc.DBL 29 No change 23
tlbmisc.PERM 29 No change 24
tlbmisc.BAD 29 No change 25
status.PIE No change 0 26
status.EH 29 No change 1 27
status.IH 35 1 No change
status.NMI 35 RNMI No change
status.IL 35 RIL No change
status.RSIE 30 35 0 No change
status.CRS 30 RRS No change
status.U 29 0 28
14 If the Nios® II processor does not have an EIC interface, external interrupts do not occur.
15 If the Nios® II processor does not have an MMU, this register is not implemented.
16 The VPN of the address triggering the exception
17 Invokes the general exception handler
18 Invokes the fast TLB miss exception handler
19 If the Nios® II processor does not have shadow register sets, this register is not implemented.
20 sstatus.SRS is set to 1 if RRS is not equal to status.CRS.
21 The address following the instruction being executed when the exception occurs
22 Set to 1 on a data access exception, set to 0 otherwise
23 Set to 1 on a double TLB miss, set to 0 otherwise
24 Set to 1 on a TLB permission violation, set to 0 otherwise
25 Set to 1 on a bad virtual address exception, set to 0 otherwise
26 Disables exceptions and nonmaskable interrupts
27 If the MMU is implemented, indicates that the processor is handling an exception.
28 Puts the processor in supervisor mode.
29 If the Nios® II processor does not have an MMU, this field is not implemented. Its value is always 0, and the processor behaves accordingly.
30 If the Nios® II processor does not have shadow register sets, this field is not implemented. Its value is always 0, and the processor behaves accordingly.
31 If the Nios® II processor does not have an MMU, TLB-related exceptions do not occur.
32 The pre-exception value
33 Saves the processor’s pre-exception status
34 If the MMU is implemented, indicates that the processor is handling an exception.
35 If the Nios® II processor does not have an EIC interface, this field is not implemented.