Nios II Classic Processor Reference Guide

ID 683620
Date 10/28/2016
Document Table of Contents

5.2. Nios II/f Core

The Nios II/f fast core is designed for high execution performance. Performance is gained at the expense of core size. The base Nios II/f core, without the memory management unit (MMU) or memory protection unit (MPU), is approximately 25% larger than the Nios II/s core. Intel FPGA designed the Nios II/f core with the following design goals in mind:
  • Maximize the instructions-per-cycle execution efficiency
  • Optimize interrupt latency
  • Maximize fMAX performance of the processor core

The resulting core is optimal for performance-critical applications, as well as for applications with large amounts of code and data, such as systems running a full-featured operating system.