Nios II Classic Processor Reference Guide

ID 683620
Date 10/28/2016
Document Table of Contents

4.5. JTAG Debug Module Tab

The JTAG Debug Module tab presents settings for configuring the JTAG debug module on the Nios II processor. You can select the debug features appropriate for your target application.
Table 60.  JTAG Debug Module Tab Parameters
Name Description
Select a Debugging Level
Debug level Refer to the "Debug Level Settings" section.
Include debugreq and debugack Signals Refer to the "Debug Signals" section.
Break Vector
Break vector memory Refer to the "Break Vector" section.
Break vector offset
Break vector
Advanced Debug Settings
OCI Onchip Trace Refer to "Advanced Debug Settings" section.
Automatically generate internal 2x clock signal

Soft processor cores such as the Nios II processor offer unique debug capabilities beyond the features of traditional fixed processors. The soft nature of the Nios II processor allows you to debug a system in development using a full-featured debug core, and later remove the debug features to conserve logic resources. For the release version of a product, you might choose to reduce the JTAG debug module functionality, or remove it altogether.

Table 61.  Debug Configuration Features
Feature Description
JTAG Target Connection Connects to the processor through the standard JTAG pins on the Altera FPGA. This connection provides the basic capabilities to start and stop the processor, and examine/edit registers and memory.
Download Software Downloads executable code to the processor’s memory via the JTAG connection.
Software Breakpoints Sets a breakpoint on instructions residing in RAM.
Hardware Breakpoints Sets a breakpoint on instructions residing in nonvolatile memory, such as flash memory.
Data Triggers Triggers based on address value, data value, or read or write cycle. You can use a trigger to halt the processor on specific events or conditions, or to activate other events, such as starting execution trace, or sending a trigger signal to an external logic analyzer. Two data triggers can be combined to form a trigger that activates on a range of data or addresses.
Instruction Trace Captures the sequence of instructions executing on the processor in real time.
Data Trace Captures the addresses and data associated with read and write operations executed by the processor in real time.
On-Chip Trace Stores trace data in on-chip memory.
Off-Chip Trace Stores trace data in an external debug probe. Off-chip trace instantiates a PLL inside the Nios II core. Off-chip trace requires a debug probe from Imagination Technologies or Lauterbach GmbH.

The following sections describe the configuration settings available.