220.127.116.11. The tlbacc Register
Issuing a wrctl instruction to the tlbacc register writes the tlbacc register with the specified value. If tlbmisc.WE = 1, the wrctl instruction also initiates a TLB write operation, which writes a TLB entry. The TLB entry written is specified by the line portion of pteaddr.VPN and the tlbmisc.WAY field. The value written is specified by the value written into tlbacc along with the values of pteaddr.VPN and tlbmisc.PID. A TLB write operation also increments tlbmisc.WAY, allowing software to quickly modify TLB entries.
Issuing a rdctl instruction to the tlbacc register returns the value of the tlbacc register. The tlbacc register is written by hardware when software triggers a TLB read operation (that is, when wrctl sets tlbmisc.RD to one).
|IG||IG is ignored by hardware and available to hold operating system specific information. Read as zero but can be written as nonzero.||Read/Write||0||Only with MMU|
|C||C is the data cacheable flag. When C = 0, data accesses are uncacheable. When C = 1, data accesses are cacheable.||Read/Write||0||Only with MMU|
|R||R is the readable flag. When R = 0, load instructions are not allowed to access memory. When R = 1, load instructions are allowed to access memory.||Read/Write||0||Only with MMU|
|W||W is the writable flag. When W = 0, store instructions are not allowed to access memory. When W = 1, store instructions are allowed to access memory.||Read/Write||0||Only with MMU|
|X||X is the executable flag. When X = 0, instructions are not allowed to execute. When X = 1, instructions are allowed to execute.||Read/Write||0||Only with MMU|
|G||G is the global flag. When G = 0, tlbmisc.PID is included in the TLB lookup. When G = 1, tlbmisc.PID is ignored and only the virtual page number is used in the TLB lookup.||Read/Write||0||Only with MMU|
|PFN||PFN is the physical frame number field. All unused upper bits must be zero.||Read/Write||0||Only with MMU|
The tlbacc register format is the recommended format for entries in the operating system page table. The IG bits are ignored by the hardware on wrctl to tlbacc and read back as zero on rdctl from tlbacc. The operating system can use the IG bits to hold operating system specific information without having to clear these bits to zero on a TLB write operation.
Did you find the information on this page useful?