Nios II Classic Processor Reference Guide

ID 683620
Date 10/28/2016
Document Table of Contents The sstatus Register

The value in the sstatus register preserves the state of the Nios® II processor during external interrupt handling. The value of sstatus is undefined at processor reset. Some bits are exclusively used by and available only to certain features of the processor.

The sstatus register is physically stored in general-purpose register r30 in each shadow register set. The normal register set does not have an sstatus register, but each shadow register set has a separate sstatus register.

Table 39.  sstatus Control Register Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Table 40.  sstatus Control Register Field Descriptions
Bit Description Access Reset Available
SRS 8 SRS is the switched register set bit. The processor sets SRS to 1 when an external interrupt occurs, if the interrupt required the processor to switch to a different register set. Read/Write Undefined EIC interface and shadow register sets only
RSIE RSIE is the register set interrupt-enable bit. When set to 1, this bit allows the processor to service external interrupts requesting the register set that is currently in use. When set to 0, this bit disallows servicing of such interrupts. Read/Write Undefined 9
NMI NMI is the nonmaskable interrupt mode bit. The processor sets NMI to 1 when it takes a nonmaskable interrupt. Read/Write Undefined 9
PRS 9 Read/Write Undefined 9
CRS 9 Read/Write Undefined 9
IL 9 Read/Write Undefined 9
IH 9 Read/Write Undefined 9
EH 9 Read/Write Undefined 9
U 9 Read/Write Undefined 9
PIE 9 Read/Write Undefined 9

The sstatus register is present in the Nios II core if both the EIC interface and shadow register sets are implemented. There is one copy of sstatus for each shadow register set.

When the Nios® II processor takes an interrupt, if a shadow register set is requested (RRS = 0) and the MMU is not in exception handler mode (status.EH = 0), the processor copies status to sstatus.

For details about RRS, refer to "Requested Register Set”.

For details about status.EH, refer to the Nios® II Processor Status After Taking Exceptions Table.

8 If the EIC interface and shadow register sets are not present, SRS always reads as 0, and the processor behaves accordingly.
9 Refer to the status Control Register Field Descriptions Table