Nios II Classic Processor Reference Guide

ID 683620
Date 10/28/2016
Document Table of Contents

4.4. MMU and MPU Settings Tab

The MMU and MPU Settings tab presents settings for configuring the MMU and MPU on the Nios II processor. You can select the features appropriate for your target application.
Table 59.  MMU and MPU Settings Tab Parameters
Name Description
Process ID (PID) bits Refer to the "MMU" section.
Optimize number of TLB entries based on device family
TLB entries
TLB Set-Associativity
Micro DTLB entries
Micro ITLB entries
Use Limit for region range Refer to the "MPU" section.
Number of data regions
Minimum data region size
Number of instruction regions
Minimum instruction region size