Nios II Classic Processor Reference Guide

ID 683620
Date 10/28/2016
Document Table of Contents

3.4.1. General-Purpose Registers

The Nios II architecture provides thirty-two 32-bit general-purpose registers, r0 through r31. Some registers have names recognized by the assembler. For example, the zero register (r0) always returns the value zero, and writing to zero has no effect. The ra register (r31) holds the return address used by procedure calls and is implicitly accessed by the call, callr and ret instructions. C and C++ compilers use a common procedure-call convention, assigning specific meaning to registers r1 through r23 and r26 through r28.

Table 11.  The Nios II General-Purpose Registers
Register Name Function Register Name Function
r0 zero 0x00000000 r16   Callee-saved register
r1 at Assembler temporary r17   Callee-saved register
r2   Return value r18   Callee-saved register
r3   Return value r19   Callee-saved register
r4   Register arguments r20   Callee-saved register
r5   Register arguments r21   Callee-saved register
r6   Register arguments r22   Callee-saved register
r7   Register arguments r23   Callee-saved register
r8   Caller-saved register r24 et Exception temporary
r9   Caller-saved register r25 bt Breakpoint temporary
r10   Caller-saved register r26 gp Global pointer
r11   Caller-saved register r27 sp Stack pointer
r12   Caller-saved register r28 fp Frame pointer
r13   Caller-saved register r29 ea Exception return address
r14   Caller-saved register r30 sstatus Status register
r15   Caller-saved register r31 ra Return address
Note: r25 is used exclusively by the JTAG debug module. It is used as the breakpoint temporary (bt) register in the normal register set. In shadow register sets, r25 is reserved.
Note: r30 is used as the breakpoint return address (ba) in the normal register set, and as the shadow register set status (sstatus) in each shadow register set. For details about sstatus, refer to The Status Register section.

For more information, refer to the Application Binary Interface chapter of the Nios® II Processor Reference Handbook.