Nios II Classic Processor Reference Guide

ID 683620
Date 10/28/2016
Document Table of Contents Instruction Cache

The instruction cache for the Nios II/s core is nearly identical to the instruction cache in the Nios II/f core. The instruction cache memory has the following characteristics:
  • Direct-mapped cache implementation
  • The instruction master port reads an entire cache line at a time from memory, and issues one read per clock cycle.
  • Critical word first
    Table 76.  Instruction Byte Address Fields
    Bit Fields
    31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
    tag line
    15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
    line offset

The size of the tag field depends on the size of the cache memory and the physical address size. The size of the line field depends only on the size of the cache memory. The offset field is always five bits (i.e., a 32-byte line). The maximum instruction byte address size is 31 bits.

The instruction cache is optional. However, excluding instruction cache from the Nios II/s core requires that the core include at least one tightly-coupled instruction memory.