3.4.2.1. The status Register
3.4.2.2. The estatus Register
3.4.2.3. The bstatus Register
3.4.2.4. The ienable Register
3.4.2.5. The ipending Register
3.4.2.6. The cpuid Register
3.4.2.7. The exception Register
3.4.2.8. The pteaddr Register
3.4.2.9. The tlbacc Register
3.4.2.10. The tlbmisc Register
3.4.2.11. The badaddr Register
3.4.2.12. The config Register
3.4.2.13. The mpubase Register
3.4.2.14. The mpuacc Register
3.7.1. Terminology
3.7.2. Exception Overview
3.7.3. Exception Latency
3.7.4. Reset Exceptions
3.7.5. Break Exceptions
3.7.6. Interrupt Exceptions
3.7.7. Instruction-Related Exceptions
3.7.8. Other Exceptions
3.7.9. Exception Processing Flow
3.7.10. Handling Nested Exceptions
3.7.11. Handling Nonmaskable Interrupts
3.7.12. Masking and Disabling Exceptions
3.7.7.1. Trap Instruction
3.7.7.2. Break Instruction
3.7.7.3. Unimplemented Instruction
3.7.7.4. Illegal Instruction
3.7.7.5. Supervisor-Only Instruction
3.7.7.6. Supervisor-Only Instruction Address
3.7.7.7. Supervisor-Only Data Address
3.7.7.8. Misaligned Data Address
3.7.7.9. Misaligned Destination Address
3.7.7.10. Division Error
3.7.7.11. Fast TLB Miss
3.7.7.12. Double TLB Miss
3.7.7.13. TLB Permission Violation
3.7.7.14. MPU Region Violation
3.9.1. Data Transfer Instructions
3.9.2. Arithmetic and Logical Instructions
3.9.3. Move Instructions
3.9.4. Comparison Instructions
3.9.5. Shift and Rotate Instructions
3.9.6. Program Control Instructions
3.9.7. Other Control Instructions
3.9.8. Custom Instructions
3.9.9. No-Operation Instruction
3.9.10. Potential Unimplemented Instructions
8.5.1. add
8.5.2. addi
8.5.3. and
8.5.4. andhi
8.5.5. andi
8.5.6. beq
8.5.7. bge
8.5.8. bgeu
8.5.9. bgt
8.5.10. bgtu
8.5.11. ble
8.5.12. bleu
8.5.13. blt
8.5.14. bltu
8.5.15. bne
8.5.16. br
8.5.17. break
8.5.18. bret
8.5.19. call
8.5.20. callr
8.5.21. cmpeq
8.5.22. cmpeqi
8.5.23. cmpge
8.5.24. cmpgei
8.5.25. cmpgeu
8.5.26. cmpgeui
8.5.27. cmpgt
8.5.28. cmpgti
8.5.29. cmpgtu
8.5.30. cmpgtui
8.5.31. cmple
8.5.32. cmplei
8.5.33. cmpleu
8.5.34. cmpleui
8.5.35. cmplt
8.5.36. cmplti
8.5.37. cmpltu
8.5.38. cmpltui
8.5.39. cmpne
8.5.40. cmpnei
8.5.41. custom
8.5.42. div
8.5.43. divu
8.5.44. eret
8.5.45. flushd
8.5.46. flushda
8.5.47. flushi
8.5.48. flushp
8.5.49. initd
8.5.50. initda
8.5.51. initi
8.5.52. jmp
8.5.53. jmpi
8.5.54. ldb / ldbio
8.5.55. ldbu / ldbuio
8.5.56. ldh / ldhio
8.5.57. ldhu / ldhuio
8.5.58. ldw / ldwio
8.5.59. mov
8.5.60. movhi
8.5.61. movi
8.5.62. movia
8.5.63. movui
8.5.64. mul
8.5.65. muli
8.5.66. mulxss
8.5.67. mulxsu
8.5.68. mulxuu
8.5.69. nextpc
8.5.70. nop
8.5.71. nor
8.5.72. or
8.5.73. orhi
8.5.74. ori
8.5.75. rdctl
8.5.76. rdprs
8.5.77. ret
8.5.78. rol
8.5.79. roli
8.5.80. ror
8.5.81. sll
8.5.82. slli
8.5.83. sra
8.5.84. srai
8.5.85. srl
8.5.86. srli
8.5.87. stb / stbio l
8.5.88. sth / sthio
8.5.89. stw / stwio
8.5.90. sub
8.5.91. subi
8.5.92. sync
8.5.93. trap
8.5.94. wrctl
8.5.95. wrprs
8.5.96. xor
8.5.97. xorhi
8.5.98. xori
8.5.47. flushi
Instruction | flush instruction cache line |
Operation | Flushes the instruction cache line associated with address rA. |
Assembler Syntax | flushi rA |
Example | flushi r6 |
Description | Ignoring the tag, flushi identifies the instruction cache line associated with the byte address in rA, and invalidates that line. If the Nios® II processor core does not have an instruction cache, the flushi instruction performs no operation. For more information about the data cache, refer to the Cache and Tightly Coupled Memory chapter of the Nios II Software Developer’s Handbook. |
Exceptions | None |
Instruction Type | R |
Instruction Fields | A = Register index of operand rA |
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
A | 0 | 0 | 0x0c | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0x0c | 0 | 0x3a |
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