Nios II Classic Processor Reference Guide

ID 683620
Date 10/28/2016
Document Table of Contents The C Flag

The C flag determines the default data cacheability of an MPU region. The C flag only applies to data regions. For instruction regions, the C bit must be written with 0 and is always read as 0.

When data cacheability is enabled on a data region, a data access to that region can be cached, if a data cache is present in the system. You can override the default cacheability and force an address to noncacheable with an ldwio or stwio instruction.

Note: The bit 31 cache bypass feature is supported when the MPU is present. Refer to the Cache memory section for more information on cache bypass.