Nios II Classic Processor Reference Guide

ID 683620
Date 10/28/2016
Document Table of Contents

5.4. Nios II/e Core

The Nios II/e economy core is designed to achieve the smallest possible core size. Intel FPGA designed the Nios II/e core with a singular design goal: reduce resource utilization any way possible, while still maintaining compatibility with the Nios II instruction set architecture. Hardware resources are conserved at the expense of execution performance. The Nios II/e core is roughly half the size of the Nios II/s core, but the execution performance is substantially lower.

The resulting core is optimal for cost-sensitive applications as well as applications that require simple control logic.