Nios II Classic Processor Reference Guide

ID 683620
Date 10/28/2016
Document Table of Contents

4.5.4. Advanced Debug Settings

Debug levels 3 and 4 support trace data collection into an on-chip memory buffer. You can set the on-chip trace buffer size to sizes from 128 to 64K trace frames, using OCI Onchip Trace. Larger buffer sizes consume more on-chip M4K RAM blocks. Every M4K RAM block can store up to 128 trace frames.
Note: The Nios II MMU does not support the JTAG debug module trace.

Debug level 4 also supports manual 2X clock signal specification. If you want to use a specific 2X clock signal in your FPGA design, turn off Automatically generate internal 2x clock signal and drive a 2X clock signal into your system manually.

For more information about trace frames, refer to the Processor Architecture chapter of the Nios II Processor Reference Handbook.