Nios II Classic Processor Reference Guide

ID 683620
Date 10/28/2016
Document Table of Contents Instruction Master Port

The Nios II instruction bus is implemented as a 32-bit Avalon® -MM master port. The instruction master port performs a single function: it fetches instructions to be executed by the processor. The instruction master port does not perform any write operations.

The instruction master port is a pipelined Avalon® -MM master port. Support for pipelined Avalon® -MM transfers minimizes the impact of synchronous memory with pipeline latency and increases the overall fMAX of the system. The instruction master port can issue successive read requests before data has returned from prior requests. The Nios® II processor can prefetch sequential instructions and perform branch prediction to keep the instruction pipe as active as possible.

The instruction master port always retrieves 32 bits of data. The instruction master port relies on dynamic bus-sizing logic contained in the system interconnect fabric. By virtue of dynamic bus sizing, every instruction fetch returns a full instruction word, regardless of the width of the target memory. Consequently, programs do not need to be aware of the widths of memory in the Nios® II processor system.

The Nios II architecture supports on-chip cache memory for improving average instruction fetch performance when accessing slower memory. Refer to the "Cache Memory" section of this chapter for details.

The Nios II architecture supports tightly-coupled memory, which provides guaranteed low-latency access to on-chip memory. Refer to the "Tightly-Coupled Memory" section of this chapter for details.