Nios II Classic Processor Reference Guide

ID 683620
Date 10/28/2016
Document Table of Contents

4.2. Caches and Memory Interfaces Tab

The Caches and Memory Interfaces tab allows you to configure the cache and tightly-coupled memory usage for the instruction and data master ports.
Table 57.  Caches and Memory Interfaces Tab Parameters
Name Description
Instruction Master
Instruction cache Refer to the "Instruction Master Settings" Section.
Burst transfers
Number of tightly coupled instruction master port(s)
Data Master
Omit data master port Refer to the "Data Master" Settings.
Data cache
Data cache line size
Burst transfers
Data cache victim buffer implementation
Number of tightly coupled instruction master port(s)

The following sections describe the configuration settings available.

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