Nios II Classic Processor Reference Guide

ID 683620
Date 10/28/2016
Public
Document Table of Contents

3.4.2.14.8. The eccinj Register

The eccinj register injects 1 and 2 bit errors to the Nios® II processor’s internal RAM blocks that support ECC. Injecting errors allows the software to test the ECC error exception handling code. The error(s) are injected in the data bits, not the parity bits. The eccinj register is only available when ECC is present.

Table 37.  eccinj Control Register Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved TLB Reserved ICDAT ICTAG RF

Software writes 0x1 to inject a 1 bit ECC error or 0x2 to inject a 2-bit ECC error to the RAM field. Hardware sets the value of the inject field to 0x0 after the error injection has occurred.

Table 38.  eccinj Control Register Field Descriptions
Field Description Access Reset Available
RF Inject an ECC error in the register file’s RAM. Read/Write 0 Only with ECC
ICTAG Inject an ECC error in the instruction cache Tag RAM. Read/Write 0 Only with ECC
ICDAT Inject an ECC error in the instruction cache data RAM. Read/Write 0 Only with ECC
TLB Inject an ECC error in the MMU TLB RAM. Errors are injected in the tag portion of the VPN field. Read/Write 0 Only with ECC

Refer to “Working with ECC” for more information about when errors are injected.