Nios II Classic Processor Reference Guide

ID 683620
Date 10/28/2016
Document Table of Contents

4.5.1. Debug Level Settings

The following debug levels are available in the JTAG Debug Module tab:
  • No Debugger
  • Level 1
  • Level 2
  • Level 3
  • Level 4

The table is a detailed list of the characteristics of each debug level. Different levels consume different amounts of on-chip resources. Certain Nios II cores have restricted debug options, and certain options require debug tools provided by Imagination Technologies™, LLC or Lauterbach GmbH.

Table 62.  JTAG Debug Module Levels
Debug Feature No Debug Level 1 Level 2 Level 3 Level 436
Logic Usage 0 300—400 LEs 800—900 LEs 2,400—2,700 LEs 3,100—3,700 LEs
On-Chip Memory Usage 0 Two M4Ks Two M4Ks Four M4Ks Four M4Ks
External I/O Pins Required37 0 0 0 0 20
JTAG Target Connection No Yes Yes Yes Yes
Download Software No Yes Yes Yes Yes
Software Breakpoints None Unlimited Unlimited Unlimited Unlimited
Hardware Execution Breakpoints 0 None 2 2 4
Data Triggers 0 None 2 2 4
On-Chip Trace 0 None None Up to 64-KB frames 38 Up to 64-KB frames
Off-Chip Trace 39 0 None None None 128-KB frames

For information about debug features available from these third parties, search for “Nios II” on the Imagination Technologies website and the Lauterbach GmbH website.

36 Level 4 requires the purchase of a software upgrade from Imagination Technologies or Lauterbach.
37 Not including the dedicated JTAG pins on the Altera FPGA.
38 An additional license from Imagination Technologies is required to use more than 16 frames.
39 Off-chip trace requires the purchase of additional hardware from Imagination Technologies or Lauterbach.