Nios II Classic Processor Reference Guide

ID 683620
Date 10/28/2016
Document Table of Contents

3.3.1. Memory Regions

The MPU contains up to 32 instruction regions and 32 data regions. Each region is defined by the following attributes:
  • Base address
  • Region type
  • Region index
  • Region size or upper address limit
  • Access permissions
  • Default cacheability (data regions only)