18.104.22.168. Micro Translation Lookaside Buffers
The translation lookaside buffer (TLB) consists of one main TLB stored in on-chip RAM and two separate micro TLBs (μTLB) for instructions μITLB) and data (μDTLB) stored in LE-based registers.
The TLBs have a configurable number of entries and are fully associative. The default configuration has 6 μDTLB entries and 4 μITLB entries. The hardware chooses the least-recently used μTLB entry when loading a new entry.
The μTLBs are not visible to software. They act as an inclusive cache of the main TLB. The processor firsts look for a hit in the μTLB. If it misses, it then looks for a hit in the main TLB. If the main TLB misses, the processor takes an exception. If the main TLB hits, the TLB entry is copied into the μTLB for future accesses.
The hardware automatically flushes the μTLB on each TLB write operation and on a wrctl to the tlbmisc register in case the process identifier (PID) has changed.
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