Nios II Classic Processor Reference Guide

ID 683620
Date 10/28/2016
Document Table of Contents

4.1.2. Multiply and Divide Settings

The Nios II/s and Nios II/f cores offer hardware multiply and divide options. You can choose the best option to balance embedded multiplier usage, logic element (LE) usage, and performance.

The Hardware multiplication type parameter for each core provides the following list:

  • DSP Block—Include DSP block multipliers in the arithmetic logic unit (ALU). This option is only selectable when targeting devices that have DSP block multipliers.
  • Embedded Multipliers—Include embedded multipliers in the ALU. This option is only present when targeting FPGA devices that have embedded multipliers.
  • Logic Elements—Include LE-based multipliers in the ALU. This option achieves high multiply performance without consuming embedded multiplier resources, but with reduced fMAX.
  • None—This option conserves logic resources by eliminating multiply hardware. Multiply operations are implemented in software.
Note: Shift operations use the multiplier. So, Hardware multiplication type affects shift instruction speed.

Turning on Hardware divide includes LE-based divide hardware in the ALU. The Hardware divide option achieves much greater performance than software emulation of divide operations.

For information about the performance effects of the hardware multiply and divide options, refer to the Nios II Core Implementation Details chapter of the Nios II Processor Reference Handbook.

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