Nios II Classic Processor Reference Guide

ID 683620
Date 10/28/2016
Document Table of Contents

4.1.3. Reset Vector

Parameters in this section select the memory module where the reset code (boot loader) resides, and the location of the reset vector (reset address). The reset vector cannot be configured until your system memory components are in place.

The Reset vector memory list, which includes all memory modules mastered by the Nios II processor, selects the reset vector memory module. In a typical system, select a nonvolatile memory module for the reset code.

Note: Qsys provides an Absolute option, which allows you to specify an absolute address in Reset vector offset. Use an absolute address when the memory storing the reset handler is located outside of the processor system and subsystems of the processor system.

Reset vector offset specifies the location of the reset vector relative to the memory module’s base address. Qsys calculates the physical address of the reset vector when you modify the memory module, the offset, or the memory module’s base address. In Qsys, Reset vector displays the read-only, calculated address. The address is always a physical address, even when an MMU is present.

For information about reset exceptions, refer to the Programming Model chapter of the Nios II Processor Reference Handbook.