Nios II Classic Processor Reference Guide

ID 683620
Date 10/28/2016
Document Table of Contents The config Register

The config register configures Nios II runtime behaviors that do not need to be preserved during exception processing (in contrast to the information in the status register).

Table 27.  config Control Register Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Table 28.  config Control Register Field Descriptions
Field Description Access Reset Available
ANI ANI is the automatic nested interrupt mode bit. If ANI is set to zero, the processor clears status.PIE on each interrupt, disabling fast nested interrupts. If ANI is set to one, the processor keeps status.PIE set to one at the time of an interrupt, enabling fast nested interrupts.

If the EIC interface and shadow register sets are not implemented in the Nios II core, ANI always reads as zero, disabling fast nested interrupts.

Read/Write 0 Only with the EIC interface and shadow register sets
ECCEXE ECCEX is the ECC error exception enable bit. When ECCEXE = 1, the Nios® II processor generates ECC error exceptions. Read/Write 0 Only with ECC
ECCEN ECCEN is the ECC enable bit. When ECCEN = 0, the Nios® II processor ignores all ECC errors. When ECCEN = 1, the Nios® II processor recovers all recoverable ECC errors. Read/Write 0 Only with ECC
PE PE is the memory protection enable bit. When PE =1, the MPU is enabled. When PE = 0, the MPU is disabled. In systems without an MPU, PE is always zero. Read/Write 0 Only with MPU