Nios II Classic Processor Reference Guide

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ID 683620
Date 10/28/2016
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Processor Architecture 3. Programming Model 4. Instantiating the Nios II Processor 5. Nios® II Core Implementation Details 6. Nios® II Processor Versions 7. Application Binary Interface 8. Instruction Set Reference
1. Introduction x
1.1. Nios® II Processor System Basics 1.2. Getting Started with the Nios II Processor 1.3. Customizing Nios® II Processor Designs 1.4. Configurable Soft Processor Core Concepts 1.5. Intel® FPGA IP Evaluation Mode Intel FPGA IP Evaluation Mode 1.6. Introduction Revision History
1.4. Configurable Soft Processor Core Concepts x
1.4.1. Configurable Soft Processor Core 1.4.2. Flexible Peripheral Set and Address Map 1.4.3. Automated System Generation
1.4.2. Flexible Peripheral Set and Address Map x
1.4.2.1. Standard Peripherals 1.4.2.2. Custom Components 1.4.2.3. Custom Instructions
2. Processor Architecture x
2.1. Processor Implementation 2.2. Register File 2.3. Arithmetic Logic Unit 2.4. Reset and Debug Signals 2.5. Exception and Interrupt Controllers 2.6. Memory and I/O Organization 2.7. JTAG Debug Module 2.8. Processor Architecture Revision History
2.3. Arithmetic Logic Unit x
2.3.1. Unimplemented Instructions 2.3.2. Custom Instructions
2.5. Exception and Interrupt Controllers x
2.5.1. Exception Controller 2.5.2. EIC Interface 2.5.3. Internal Interrupt Controller
2.6. Memory and I/O Organization x
2.6.1. Instruction and Data Buses 2.6.2. Cache Memory 2.6.3. Tightly-Coupled Memory 2.6.4. Address Map 2.6.5. Memory Management Unit 2.6.6. Memory Protection Unit
2.6.1. Instruction and Data Buses x
2.6.1.1. Memory and Peripheral Access 2.6.1.2. Instruction Master Port 2.6.1.3. Data Master Port 2.6.1.4. Shared Memory for Instructions and Data
2.6.2. Cache Memory x
2.6.2.1. Configurable Cache Memory Options 2.6.2.2. Effective Use of Cache Memory 2.6.2.3. Cache Bypass Methods
2.6.2.3. Cache Bypass Methods x
2.6.2.3.1. I/O Load and Store Instructions Method 2.6.2.3.2. The Bit-31 Cache Bypass Method
2.6.3. Tightly-Coupled Memory x
2.6.3.1. Accessing Tightly-Coupled Memory 2.6.3.2. Effective Use of Tightly-Coupled Memory
2.7. JTAG Debug Module x
2.7.1. JTAG Target Connection 2.7.2. Download and Execute Software 2.7.3. Software Breakpoints 2.7.4. Hardware Breakpoints 2.7.5. Hardware Triggers 2.7.6. Trace Capture
2.7.5. Hardware Triggers x
2.7.5.1. Armed Triggers 2.7.5.2. Triggering on Ranges of Values
2.7.6. Trace Capture x
2.7.6.1. Execution vs. Data Trace 2.7.6.2. Trace Frames
3. Programming Model x
3.1. Operating Modes 3.2. Memory Management Unit 3.3. Memory Protection Unit 3.4. Registers 3.5. Working with the MPU 3.6. Working with ECC 3.7. Exception Processing 3.8. Memory and Peripheral Access 3.9. Instruction Set Categories 3.10. Programming Model Revision History
3.1. Operating Modes x
3.1.1. Supervisor Mode 3.1.2. User Mode
3.2. Memory Management Unit x
3.2.1. Recommended Usage 3.2.2. Memory Management 3.2.3. Address Space and Memory Partitions 3.2.4. TLB Organization 3.2.5. TLB Lookups
3.2.2. Memory Management x
3.2.2.1. Virtual Addressing 3.2.2.2. Memory Protection
3.2.3. Address Space and Memory Partitions x
3.2.3.1. Virtual Memory Address Space 3.2.3.2. Physical Memory Address Space 3.2.3.3. Data Cacheability
3.3. Memory Protection Unit x
3.3.1. Memory Regions 3.3.2. Overlapping Regions 3.3.3. Enabling the MPU
3.3.1. Memory Regions x
3.3.1.1. Base Address 3.3.1.2. Region Type 3.3.1.3. Region Index 3.3.1.4. Region Size or Upper Address Limit 3.3.1.5. Access Permissions 3.3.1.6. Default Cacheability
3.4. Registers x
3.4.1. General-Purpose Registers 3.4.2. Control Registers 3.4.3. Shadow Register Sets
3.4.2. Control Registers x
3.4.2.1. The status Register 3.4.2.2. The estatus Register 3.4.2.3. The bstatus Register 3.4.2.4. The ienable Register 3.4.2.5. The ipending Register 3.4.2.6. The cpuid Register 3.4.2.7. The exception Register 3.4.2.8. The pteaddr Register 3.4.2.9. The tlbacc Register 3.4.2.10. The tlbmisc Register 3.4.2.11. The badaddr Register 3.4.2.12. The config Register 3.4.2.13. The mpubase Register 3.4.2.14. The mpuacc Register
3.4.2.10. The tlbmisc Register x
3.4.2.10.1. The RD Flag 3.4.2.10.2. The WE Flag 3.4.2.10.3. The WAY Field 3.4.2.10.4. The PID Field 3.4.2.10.5. The DBL Flag 3.4.2.10.6. The BAD Flag 3.4.2.10.7. The PERM Flag 3.4.2.10.8. The D Flag
3.4.2.14. The mpuacc Register x
3.4.2.14.1. The MASK Field 3.4.2.14.2. The LIMIT Field 3.4.2.14.3. The C Flag 3.4.2.14.4. The MT Flag 3.4.2.14.5. The PERM Field 3.4.2.14.6. The RD Flag 3.4.2.14.7. The WR Flag 3.4.2.14.8. The eccinj Register
3.4.3. Shadow Register Sets x
3.4.3.1. The sstatus Register 3.4.3.2. Initialization with Shadow Register Sets
3.4.3.1. The sstatus Register x
3.4.3.1.1. Changing Register Sets 3.4.3.1.2. Stacks and Shadow Register Sets
3.5. Working with the MPU x
3.5.1. MPU Region Read and Write Operations 3.5.2. MPU Initialization 3.5.3. Debugger Access
3.6. Working with ECC x
3.6.1. Enabling ECC 3.6.2. Handling ECC Errors 3.6.3. Injecting ECC Errors
3.6.1. Enabling ECC x
3.6.1.1. Disabling ECC
3.6.3. Injecting ECC Errors x
3.6.3.1. Instruction Cache Tag RAM 3.6.3.2. Instruction Cache Data RAM 3.6.3.3. Register File RAM Blocks 3.6.3.4. MMU TLB RAM
3.7. Exception Processing x
3.7.1. Terminology 3.7.2. Exception Overview 3.7.3. Exception Latency 3.7.4. Reset Exceptions 3.7.5. Break Exceptions 3.7.6. Interrupt Exceptions 3.7.7. Instruction-Related Exceptions 3.7.8. Other Exceptions 3.7.9. Exception Processing Flow 3.7.10. Handling Nested Exceptions 3.7.11. Handling Nonmaskable Interrupts 3.7.12. Masking and Disabling Exceptions
3.7.3. Exception Latency x
3.7.3.1. Interrupt Latency
3.7.5. Break Exceptions x
3.7.5.1. Processing a Break 3.7.5.2. Understanding Register Usage 3.7.5.3. Returning From a Break
3.7.6. Interrupt Exceptions x
3.7.6.1. External Interrupt Controller Interface 3.7.6.2. Internal Interrupt Controller
3.7.6.1. External Interrupt Controller Interface x
3.7.6.1.1. Requested Handler Address 3.7.6.1.2. Requested Interrupt Level 3.7.6.1.3. Requested Register Set 3.7.6.1.4. Requested NMI Mode 3.7.6.1.5. Shadow Register Sets
3.7.7. Instruction-Related Exceptions x
3.7.7.1. Trap Instruction 3.7.7.2. Break Instruction 3.7.7.3. Unimplemented Instruction 3.7.7.4. Illegal Instruction 3.7.7.5. Supervisor-Only Instruction 3.7.7.6. Supervisor-Only Instruction Address 3.7.7.7. Supervisor-Only Data Address 3.7.7.8. Misaligned Data Address 3.7.7.9. Misaligned Destination Address 3.7.7.10. Division Error 3.7.7.11. Fast TLB Miss 3.7.7.12. Double TLB Miss 3.7.7.13. TLB Permission Violation 3.7.7.14. MPU Region Violation
3.7.9. Exception Processing Flow x
3.7.9.1. Processing General Exceptions 3.7.9.2. Exception Flow with the EIC Interface 3.7.9.3. Exception Flow with the Internal Interrupt Controller 3.7.9.4. Exceptions and Processor Status
3.7.10. Handling Nested Exceptions x
3.7.10.1. Nested Exceptions with the Internal Interrupt Controller 3.7.10.2. Nested Exceptions with an External Interrupt Controller
3.7.12. Masking and Disabling Exceptions x
3.7.12.1. Disabling Maskable Interrupts 3.7.12.2. Masking Interrupts with an External Interrupt Controller 3.7.12.3. Masking Interrupts with the Internal Interrupt Controller 3.7.12.4. Returning From Interrupt and Instruction-Related Exceptions
3.7.12.4. Returning From Interrupt and Instruction-Related Exceptions x
3.7.12.4.1. Return Address Considerations
3.8. Memory and Peripheral Access x
3.8.1. Cache Memory
3.8.1. Cache Memory x
3.8.1.1. Virtual Address Aliasing
3.9. Instruction Set Categories x
3.9.1. Data Transfer Instructions 3.9.2. Arithmetic and Logical Instructions 3.9.3. Move Instructions 3.9.4. Comparison Instructions 3.9.5. Shift and Rotate Instructions 3.9.6. Program Control Instructions 3.9.7. Other Control Instructions 3.9.8. Custom Instructions 3.9.9. No-Operation Instruction 3.9.10. Potential Unimplemented Instructions
4. Instantiating the Nios II Processor x
4.1. Core Nios II Tab 4.2. Caches and Memory Interfaces Tab 4.3. Advanced Features Tab 4.4. MMU and MPU Settings Tab 4.5. JTAG Debug Module Tab 4.6. Custom Instruction Tab 4.7. The Quartus Prime IP File 4.8. Document Revision History
4.1. Core Nios II Tab x
4.1.1. Core Selection 4.1.2. Multiply and Divide Settings 4.1.3. Reset Vector 4.1.4. General Exception Vector 4.1.5. Memory Management Unit Settings 4.1.6. Memory Protection Unit Settings
4.1.5. Memory Management Unit Settings x
4.1.5.1. Fast TLB Miss Exception Vector
4.2. Caches and Memory Interfaces Tab x
4.2.1. Instruction Master Settings 4.2.2. Data Master Settings
4.3. Advanced Features Tab x
4.3.1. Reset Signals 4.3.2. Control Registers 4.3.3. Exception Checking 4.3.4. Interrupt Controller Interfaces 4.3.5. Shadow Register Sets 4.3.6. HardCopy Compatible 4.3.7. ECC
4.4. MMU and MPU Settings Tab x
4.4.1. MMU 4.4.2. MPU
4.5. JTAG Debug Module Tab x
4.5.1. Debug Level Settings 4.5.2. Debug Signals 4.5.3. Break Vector 4.5.4. Advanced Debug Settings
4.6. Custom Instruction Tab x
4.6.1. Altera-Provided Custom Instructions
4.6.1. Altera-Provided Custom Instructions x
4.6.1.1. Floating Point Hardware 2 Custom Instruction 4.6.1.2. Floating-Point Hardware Custom Instruction 4.6.1.3. Bitswap Custom Instruction
5. Nios® II Core Implementation Details x
5.1. Device Family Support 5.2. Nios II/f Core 5.3. Nios II/s Core 5.4. Nios II/e Core 5.5. Nios® II Core Implementation Details Revision History
5.2. Nios II/f Core x
5.2.1. Overview 5.2.2. Arithmetic Logic Unit 5.2.3. Memory Access 5.2.4. Tightly-Coupled Memory 5.2.5. Memory Management Unit 5.2.6. Memory Protection Unit 5.2.7. Execution Pipeline 5.2.8. Instruction Performance 5.2.9. Exception Handling 5.2.10. ECC 5.2.11. JTAG Debug Module
5.2.2. Arithmetic Logic Unit x
5.2.2.1. Multiply and Divide Performance 5.2.2.2. Shift and Rotate Performance
5.2.3. Memory Access x
5.2.3.1. Instruction and Data Master Ports 5.2.3.2. Instruction and Data Caches
5.2.3.2. Instruction and Data Caches x
5.2.3.2.1. Instruction Cache 5.2.3.2.2. Data Cache 5.2.3.2.3. Bursting
5.2.5. Memory Management Unit x
5.2.5.1. Micro Translation Lookaside Buffers
5.2.7. Execution Pipeline x
5.2.7.1. Pipeline Stalls 5.2.7.2. Branch Prediction
5.2.9. Exception Handling x
5.2.9.1. External Interrupt Controller Interface
5.3. Nios II/s Core x
5.3.1. Overview 5.3.2. Arithmetic Logic Unit 5.3.3. Memory Access 5.3.4. Tightly-Coupled Memory 5.3.5. Execution Pipeline 5.3.6. Instruction Performance 5.3.7. Exception Handling 5.3.8. JTAG Debug Module
5.3.2. Arithmetic Logic Unit x
5.3.2.1. Multiply and Divide Performance 5.3.2.2. Shift and Rotate Performance
5.3.3. Memory Access x
5.3.3.1. Instruction and Data Master Ports 5.3.3.2. Instruction Cache
5.3.5. Execution Pipeline x
5.3.5.1. Pipeline Stalls 5.3.5.2. Branch Prediction
5.4. Nios II/e Core x
5.4.1. Overview 5.4.2. Arithmetic Logic Unit 5.4.3. Memory Access 5.4.4. Instruction Execution Stages 5.4.5. Instruction Performance 5.4.6. Exception Handling 5.4.7. JTAG Debug Module
6. Nios® II Processor Versions x
6.1. Nios II Versions Revision History 6.2. Architecture Revisions 6.3. Core Revisions 6.4. JTAG Debug Module Revisions 6.5. Nios® II Processor Versions Revision History
6.3. Core Revisions x
6.3.1. Nios II/f Core 6.3.2. Nios II/s Core 6.3.3. Nios II/e Core
7. Application Binary Interface x
7.1. Data Types 7.2. Memory Alignment 7.3. Register Usage 7.4. Stacks 7.5. Arguments and Return Values 7.6. DWARF-2 Definition 7.7. Object Files 7.8. Relocation 7.9. ABI for Linux Systems 7.10. Development Environment 7.11. Application Binary Interface Revision History
7.4. Stacks x
7.4.1. Frame Pointer Elimination 7.4.2. Call Saved Registers 7.4.3. Further Examples of Stacks 7.4.4. Function Prologues
7.4.3. Further Examples of Stacks x
7.4.3.1. Stack Frame for a Function With alloca() 7.4.3.2. Stack Frame for a Function with Variable Arguments 7.4.3.3. Stack Frame for a Function with Structures Passed By Value
7.4.4. Function Prologues x
7.4.4.1. Prologue Variations
7.5. Arguments and Return Values x
7.5.1. Arguments 7.5.2. Return Values
7.9. ABI for Linux Systems x
7.9.1. Linux Toolchain Relocation Information 7.9.2. Linux Function Calls 7.9.3. Linux Operating System Call Interface 7.9.4. Linux Process Initialization 7.9.5. Linux Position-Independent Code 7.9.6. Linux Program Loading and Dynamic Linking 7.9.7. Linux Conventions
7.9.1. Linux Toolchain Relocation Information x
7.9.1.1. Copy Relocation 7.9.1.2. Jump Slot Relocation 7.9.1.3. Thread-Local Storage
7.9.6. Linux Program Loading and Dynamic Linking x
7.9.6.1. Global Offset Table 7.9.6.2. Function Addresses 7.9.6.3. Procedure Linkage Table 7.9.6.4. Linux Program Interpreter 7.9.6.5. Linux Initialization and Termination Functions
7.9.7. Linux Conventions x
7.9.7.1. System Calls 7.9.7.2. Userspace Breakpoints 7.9.7.3. Atomic Operations 7.9.7.4. Processor Requirements
8. Instruction Set Reference x
8.1. Word Formats 8.2. Instruction Opcodes 8.3. Assembler Pseudo-Instructions 8.4. Assembler Macros 8.5. Instruction Set Reference 8.6. Instruction Set Reference Revision History
8.1. Word Formats x
8.1.1. I-Type 8.1.2. R-Type 8.1.3. J-Type
8.5. Instruction Set Reference x
8.5.1. add 8.5.2. addi 8.5.3. and 8.5.4. andhi 8.5.5. andi 8.5.6. beq 8.5.7. bge 8.5.8. bgeu 8.5.9. bgt 8.5.10. bgtu 8.5.11. ble 8.5.12. bleu 8.5.13. blt 8.5.14. bltu 8.5.15. bne 8.5.16. br 8.5.17. break 8.5.18. bret 8.5.19. call 8.5.20. callr 8.5.21. cmpeq 8.5.22. cmpeqi 8.5.23. cmpge 8.5.24. cmpgei 8.5.25. cmpgeu 8.5.26. cmpgeui 8.5.27. cmpgt 8.5.28. cmpgti 8.5.29. cmpgtu 8.5.30. cmpgtui 8.5.31. cmple 8.5.32. cmplei 8.5.33. cmpleu 8.5.34. cmpleui 8.5.35. cmplt 8.5.36. cmplti 8.5.37. cmpltu 8.5.38. cmpltui 8.5.39. cmpne 8.5.40. cmpnei 8.5.41. custom 8.5.42. div 8.5.43. divu 8.5.44. eret 8.5.45. flushd 8.5.46. flushda 8.5.47. flushi 8.5.48. flushp 8.5.49. initd 8.5.50. initda 8.5.51. initi 8.5.52. jmp 8.5.53. jmpi 8.5.54. ldb / ldbio 8.5.55. ldbu / ldbuio 8.5.56. ldh / ldhio 8.5.57. ldhu / ldhuio 8.5.58. ldw / ldwio 8.5.59. mov 8.5.60. movhi 8.5.61. movi 8.5.62. movia 8.5.63. movui 8.5.64. mul 8.5.65. muli 8.5.66. mulxss 8.5.67. mulxsu 8.5.68. mulxuu 8.5.69. nextpc 8.5.70. nop 8.5.71. nor 8.5.72. or 8.5.73. orhi 8.5.74. ori 8.5.75. rdctl 8.5.76. rdprs 8.5.77. ret 8.5.78. rol 8.5.79. roli 8.5.80. ror 8.5.81. sll 8.5.82. slli 8.5.83. sra 8.5.84. srai 8.5.85. srl 8.5.86. srli 8.5.87. stb / stbio l 8.5.88. sth / sthio 8.5.89. stw / stwio 8.5.90. sub 8.5.91. subi 8.5.92. sync 8.5.93. trap 8.5.94. wrctl 8.5.95. wrprs 8.5.96. xor 8.5.97. xorhi 8.5.98. xori
1. Introduction
2. Processor Architecture
3. Programming Model
4. Instantiating the Nios II Processor
5. Nios® II Core Implementation Details
6. Nios® II Processor Versions
7. Application Binary Interface
8. Instruction Set Reference

2.3.3.1. Floating Point Custom Instruction 2 Component

You can add floating-point custom instructions to any Nios II processor design. The floating-point division hardware requires more resources than the other instructions. The Floating Point Hardware 2 component supports the following single-precision floating-point operations:
  • Add
  • Subtract
  • Multiply
  • Divide
  • Square root
  • Comparison
  • Integer conversion
  • Minimum
  • Maximum
  • Negate
  • Absolute

Other floating-point operations (including double-precision operations) are implemented with software emulation. The component requires the following device resources:

  • ~2,500 4-input LEs
  • 9 x 9 bit multipliers
  • 3x M9K memories

In the following table, a and b are assumed to be single-precision floating-point values.

Table 4.  Floating Point Custom Instruction 2 Operation Summary
Operation 2 N 3 Cycles Result Subnormal Rounding GCC Inference
fdivs 255 16 a ÷ b Flush to 0 Nearest a / b
fsubs 254 5 a – b Flush to 0 Faithful a – b
fadds 253 5 a + b Flush to 0 Faithful a + b
fmuls 252 4 a x b Flush to 0 Faithful a * b
fsqrts 251 8 Flush to 0 Faithful sqrtf() 4
floatis 250 4 int_to_float(a) Not applicable Not applicable Casting
fixsi 249 2 float_to_int(a) Flush to 0 Truncation Casting
round 248 2 float_to_int(a) Flush to 0 Nearest lroundf()4
Reserved 234 to 247 Undefined Undefined      
fmins 233 1 (a < b) ? a : b Supported None fminf()4
fmaxs 232 1 (a < b) ? b : a Supported None fmaxf()4
fcmplts 231 1 (a < b) ? 1 : 0 Supported None a < b
fcmples 230 1 (a ≤ b) ? 1 : 0 Supported None a <= b
fcmpgts 229 1 (a > b) ? 1 : 0 Supported None a > b
fcmpges 228 1 (a ≥ b) ? 1 : 0 Supported None a >= b
fcmpeqs 227 1 (a = b) ? 1 : 0 Supported None a == b
fcmpnes 226 1 (a ≠ b) ? 1 : 0 Supported None a != b
fnegs 225 1 -a Supported None -a
fabss 224 1 |a| Supported None fabsf()

The cycles column specifies the number of cycles required to execute the instruction. A combinatorial custom instruction takes 1 cycle. A multi-cycle custom instruction requires at least 2 cycles. An N-cycle multi-cycle custom instruction has N - 2 register stages inside the custom instruction because the Nios II processor registers the result from the custom instruction and allows another cycle for g wire delays in the source operand bypass multiplexers. The number of cycles does not include the extra cycles (maximum of 2) that an instruction following the multi-cycle custom instruction is stalled by the Nios II/f if the instruction uses the result within 2 cycles. These extra cycles occur because multi-cycle instructions are late result instructions

In Qsys, the Floating Point Hardware 2 component is under Embedded Processors on the Component Library tab.

The Nios II Software Build Tools (SBT) include software support for the Floating Point Custom Instruction 2 component. When the Floating Point Custom Instruction 2 component is present in hardware, the Nios II compiler compiles the software codes to use the custom instructions for floating point operations.

2 These names match the names of the corresponding GCC command-line options except for round, which GCC does not support.
3 Specifies the 8 bit fixed custom instruction for the operation.
4 Nios II GCC version 4.7.3 is not able to reliably replace calls to newlib floating-point functions with the equivalent custom instruction even though it has -mcustom-<operation> command-line options and pragma support for these operations. Instead, the custom instruction must be invoked directly using the GCC __builtin_custom_* facility. The Floating Point Custom Instruction 2 component includes a C header file that provides the required #define macros to invoke the custom instruction directly.
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