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36.4. Warp IP Registers
|Register Name||Offset Address||Access Type||Description|
|vid_pid||0x000||RO||Warp IP product and vendor ID|
|version_number||0x004||RO||The version for this release of the Warp IP|
|pip||0x010||RO||Indicates the value of pixels in parallel parameter|
|color_planes||0x014||RO||Indicates the value of number of color planes parameter|
|cps||0x018||RO||Indicates the value of bits per color sample parameter|
|num_engines||0x01C||RO||Indicates the value of number of engines parameter|
|max_input_width||0x020||RO||Indicates the value of maximum input video width parameter|
|max_output_width||0x024||RO||Indicates the value of maximum output video width parameter|
|memory_buffer_size||0x028||RO||Indicates the value of memory frame buffer size parameter|
|easy_warp||0x02C||RO||Indicates the value of Use easy warp parameter|
|single_memory_bounce||0x030||RO||Indicates the value of Use single memory bounce parameter|
|cache_blocks||0x034||RO||Indicates the value of Cache blocks per engine parameter|
|int_control||0x170||RW||Turns on the interrupt|
|int_status||0x174||RW1C||Read interrupt status and clear interrupt|
|31:16||VID||Vendor ID that returns a value of 0x6AF7|
|15:0||PID||Warp product ID that returns a value of 0x016F|
|31:0||Version Number||The version number of the Warp IP|
|31:0||Pixels in Parallel||The pixel in parallel parameter. Returns a value of 1 or 2.|
|31:0||Number of Color Planes||The number of color planes parameter. Returns a value of 3.|
|31:0||Bits per Color Sample||The bits per color sample parameter. Returns a value of 10.|
|31:0||Number of Engines||The number of engines parameter. Returns a value of 1 or 2.|
|31:0||Maximum input video width||The maximum input video width parameter. Returns a value of 2048 or 3840.|
|31:0||Maximum output video width||The maximum output video width parameter. Returns a value of 2048 or 3840.|
|31:0||Memory frame buffer size||
The memory frame buffer size parameter. Returns a value of 0, 1 or 2.
0 = SD, 1=HD and 2=UHD
|31:0||Use easy warp||The Use easy warp parameter. Returns a value of 0 or 1.|
|31:0||Single memory Bounce||The Use single memory bounce parameter. Returns a value of 0 or 1.|
|31:0||Cache blocks||The Cache blocks per engine parameter. Returns a value of 256, 512 or 1024.|
|0||Interrupt Enable||Setting this bit to 1 enables the interrupt. Setting to 0 disables the interrupt.|
Reading from this bit returns the status of the interrupt.
Writing a 1 to this bit clears the interrupt. Once triggered, the interrupt remains set until it is cleared by writing a 1 to this bit.
Debug and Measurement Registers
When you turn on Enable Debug Registers in the configuration settings of the Warp IP, a set of read only registers are available that provide various debug and measurement readings. The registers provide information useful during system bring up and debug and are accessed using the software API.
The available measurements are:
- Input section:
- Output section
- Engine section
- General section
| Input Section
The IP reads the debug registers relating to the input section of the Warp IP using the intel_vvp_warp_get_input_debug_register () API call.
A count of the number of frames that have started at the input of the Warp IP. The last frame counted may be incomplete.
This counter can indicate the video activity at the input of the Warp IP. Sampling this count periodically indicates frame rate. A static count indicates that the upstream pipeline to the Warp IP is not producing video data.
The number of axi4s_vid_in_0_clock cycles seen between the last two start of frames seen at the input.
Use this counter to indicate the frame rate by comparing its value with the input clock frequency. If the value from this register varies greatly, it indicates an unstable processing pipeline upstream of the Warp IP.
The debug registers relating to the output section of the Warp IP are read using the intel_vvp_warp_get_output_debug_register () API call.
A count of the number of frames that have started at the output. The last frame counted may be incomplete.
This counter can indicate the video activity at the output of the Warp IP. Sampling this count periodically gives an indication of frame rate and a static count indicates that the downstream pipeline from the Warp IP is blocked and not accepting video data.
The number of axi4s_vid_out_0_clock cycles seen between the last two start of frames seen at the output.
This counter can indicate the frame rate by comparing its value with the output clock frequency. If the value from this register varies wildly, it indicates an unstable processing pipeline downstream of the Warp IP.
The debug registers relating to the engine section of the Warp IP are read using the intel_vvp_warp_get_engine_debug_register () API call.
A count of the number of frames that have started to be processed by the engine being referenced. The processing of the last frame counted may be in progress.
This counter is useful for indicating the video activity within the Warp IP. It gives an indication that the Warp IP is set up and that the engine is configured to process correctly.
The number of core_clock cycles seen between the last two start of frames seen at the engine.
This counter is useful for confirming that the core_clock is set correctly given the expected frame rate. It is also useful for comparing against the ENGINE_BUSY _CYCLES value as an indication of how busy the engine is.
The number of core_clock cycles for which the engine actively processes video data during the last frame. The counter starts when the processing of a frame begins and continues until either the IP completes the frame or encounters the start of the next frame. For the latter the engine fails to complete the processing of the frame in time, refer to the ENGINE_FAILED_TO_COMPLETE_FRAME status indicator.
When compared to the ENGINE_FRAME_PERIOD, the value of ENGINE_BUSY_CYCLES gives an indication of how busy an engine is during the processing of a frame.
The number of core_clock cycles between the start of the last input frame and the start of the engine’s processing phase.
Use this counter for low latency behavior to determine if you have enough delay when programming the low latency settings. It also indicates the input and output frame synchronization that is a requirement for correct low latency behavior. This delay must be stable for low latency IPs to work correctly. If the IP does not see a stable value, the delay is changing over time, which indicates the input to output frame synchronization may not be operating correctly.
A sticky flag that indicates that the engine has failed to complete the processing of a frame in the required frame period. The flag is cleared each time it is interrogated.
The IP sets this to indicate that the engine has not had sufficient time to process the video frame as required and image corruption occurs. The most likely reason is insufficient memory bandwidth available to the engine. Insufficient memory bandwidth gives processing stalls either while waiting for read data to return or stalls while blocked waiting for write data is sent out.
This value is only relevant when Use single memory bounce is on.
The lower 16 bits of the value indicate the lowest buffering level the IP reaches during the processing of the previous frame. The buffering level is the difference between the write position and the read position of the current cache accesses. If this value is 0, it indicates that the engine stalls during the processing of the frame. This stall can give unstable output video when Use single memory bounce is on.
The upper 16 bits of the value is the output line at which the IP reaches the lowest buffering level. They indicate at which point in the transform this output line occurs.
|ENGINE_CACHE_LOADS||The number of cache loads the IP produces while the IP processes the previous frame. Each cache load reads a 16x8 pixel block (128 pixels in total). The total number of cache reads indicates the memory bandwidth load that the current warp transform is placing on the memory.|
The debug registers relating to the general section of the Warp IP are read using the intel_vvp_warp_get debug_register () API call.
Indicates the number of internal requests that queue at any one time for each of the write accesses through the Warp IP’s memory controller. The IP stores each queue depth value as a byte in the 32-bit data word returned by the read to this register. The IP has a number of queues depending on the configuration (Separate Queue Values (Write Accesses)).
|MEM_RD_QUEUES0 and MEM_RD_QUEUES1||
Indicates the number of internal requests that queue at any one time for each of the read accesses through the Warp IP’s memory controller. The IP has two 32 bit registers for access to the read queue depths. Each individual queue depth value is stored as a nibble in the 32 bit data word returned by a read to one of these registers. The IP has a number of queues depending on the configuration (Separate Queue Values (Read Accesses))
|Queue||Use Easy Warp or Use Single Memory Bounce are On||Single Engine||Dual Engine|
|Engine 0 Write||N/A||MEM_WR_QUEUES0[15:8]||MEM_WR_QUEUES0[15:8]|
|Engine 1 Write||N/A||N/A||MEM_WR_QUEUES0[23:16]|
|Queue||Easy Warp||Single Engine||Dual Engine|
|Engine 0 Video||N/A||MEM_RD_QUEUES0[7:4]||MEM_RD_QUEUES0[7:4]|
|Engine 0 Coeff0||N/A||MEM_RD_QUEUES0[11:8]||MEM_RD_QUEUES0[11:8]|
|Engine 0 Coeff1||N/A||MEM_RD_QUEUES0[15:12]||MEM_RD_QUEUES0[15:12]|
|Engine 0 Coeff2||N/A||MEM_RD_QUEUES0[19:16]||MEM_RD_QUEUES0[19:16]|
|Engine 1 Video||N/A||N/A||MEM_RD_QUEUES0[23:20]|
|Engine 1 Coeff0||N/A||N/A||MEM_RD_QUEUES0[27:24]|
|Engine 1 Coeff1||N/A||N/A||MEM_RD_QUEUES0[31:28]|
|Engine 1 Coeff2||N/A||N/A||MEM_RD_QUEUES1[3:0]|
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