Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 9/30/2022
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Generic Crosspoint Intel® FPGA IP 23. Genlock Signal Router Intel® FPGA IP 24. Guard Bands Intel® FPGA IP 25. Interlacer Intel® FPGA IP 26. Mixer Intel® FPGA IP 27. Pixels in Parallel Converter Intel® FPGA IP 28. Scaler Intel® FPGA IP 29. Stream Cleaner Intel® FPGA IP 30. Switch Intel® FPGA IP 31. Tone Mapping Operator Intel® FPGA IP 32. Test Pattern Generator Intel® FPGA IP 33. Video Frame Buffer Intel® FPGA IP 34. Video Streaming FIFO Intel® FPGA IP 35. Video Timing Generator Intel® FPGA IP 36. Warp Intel® FPGA IP 37. Design Security 38. Document Revision History for Video and Vision Processing Suite User Guide

14.3.1. Clocked Video to Full-Raster Converter Interfaces

The Clocked Video to Full-Raster Converter IP has three functional interfaces

  • Clocked video data input interface for video IOs.
  • Full-raster data output interface for video IOs
  • Avalon memory-mapped CPU interface
Table 181.  Clocks and Resets
Name Direction Width Description
vid_clock Input 1

When you select Lite and CVO for CV Bus style, vid_clock is the video clock for the lite and clocked video output inputs, and the streaming full-raster output.

When you select CVI for CV Bus style, vid_clock is a dummy signal retained for Platform Designer connectivity. The IP uses the video clock included in the cv_vid_in conduit.

vid_reset Input 1 Reset for vid_clock domain.
cpu_clock Input 1 Optional control interface clock.
cpu_reset Input 1 Optional control interface reset.
cv_clk_out Output 1 A copy of the video clock the IP uses.
Table 182.   Control Interface This interface is only available if you select True for Memory-mapped control interface.
Name Direction Width Description
av_mm_cpu_agent_address Input 7 Control agent port Avalon memory-mapped address bus. Specifies a word offset into the slave address space.
av_mm_cpu_agent_read Input 1 Control agent port Avalon memory-mapped read signal. When you assert this signal, the control port drives new data onto the read data bus.
av_mm_cpu_agent_readdata Output 32 Control agent port Avalon memory-mapped read data bus. These output lines are used for read transfers
av_mm_cpu_agent_waitrequest Output 1 Control agent port Avalon memory-mapped wait request bus. This signal indicates that the slave is stalling the master transaction.
av_mm_cpu_agent_write Input 1 Control agent port Avalon memory-mapped write signal. When you assert this signal, the control port accepts new data from the write data bus.
av_mm_cpu_agent_writedata Input 32 Control agent port Avalon memory-mapped write data bus. These input lines are used for write transfers.
av_mm_cpu_agent_byteenable Input 4 Control agent port Avalon memory-mapped byte enable bus. These lines indicate which bytes are selected for write and read transactions.
Table 183.  Streaming full-raster video interface
Name Direction Width Description
axi4s_fr_vid_out_tvalid Output 1 AXI4-S full-raster data valid.
axi4s_fr_vid_out_tready Input 1 Optional AXI4-S full-raster data ready.
axi4s_fr_vid_out_tdata Output 23 AXI4-S full-raster data in.
axi4s_fr_vid_out_tlast Output 1 AXI4-S end of full-raster packet .
axi4s_fr_vid_out_tuser[0] Output 24 AXI4-S start of full-raster video frame.
Table 184.  CV-Lite Streaming Video InterfaceThis interface is only available if you select Lite for CV Bus Style.
Name Direction Width Description
cv_vid_in_h Input Pixels in parallel When 1, the video is in a horizontal blanking.
cv_vid_in_v Input Pixels in parallel When 1, the video is in a vertical blanking.
cv_vid_in_h_sync Input Pixels in parallel When 1, the video is in a horizontal synchronization period.
cv_vid_in_v_sync Input Pixels in parallel When 1, the video is in a vertical synchronization period.
cv_vid_in_f Input Pixels in parallel When 1, the video is interlaced and in field 1. When 0, the video is either progressive or interlaced and in field 0.
cv_vid_in_active Input Pixels in parallel When asserted, the video is in an active picture period (not horizontal or vertical blanking). Drive this signal for the correct operation of the IPs.
cv_vid_in_data Input 25 Pixel data.
cv_vid_in_valid Input 1 When 1, the input is valid.
cv_vid_in_ready Output 1 When 1, the IP can accept new data. When 0, no new data can be accepted.
Table 185.  Clocked Video Input Streaming Video InterfaceThis interface is only available if you select CVI for CV Bus Style.
 
Port Name Direction Width Description
cv_vid_in_vid_clk Input 1 The pixel synchronous clock
cv_vid_in_vid_h_sync Input Pixels in parallel When 1, the video is in a horizontal blanking or synchronization period.
cv_vid_in_vid_v_sync Input Pixels in parallel When 1, the video is in a vertical blanking or synchronization period.
cv_vid_in_vid_f Input Pixels in parallel When 1, the video is interlaced and in field 1. When 0, the video is either progressive or interlaced and in field 0.
cv_vid_in_vid_data Input 26 Pixel Data
cv_vid_in_vid_de Input Pixels in parallel When asserted, the video is in an active picture period (not horizontal or vertical blanking). This signal must be driven for correct operation of the IP cores.
cv_vid_in_vid_datavalid Input 1 When 1, the input is valid
cv_vid_in_vid_locked Input 1 Unused legacy signal.
cv_vid_in_vid_hd_sdn Input 1 Unused legacy signal.
cv_vid_in_vid_std Input User Specified Unused legacy signal.
cv_vid_in_vid_color_encoding Input 8 Unused legacy signal.
cv_vid_in_vid_bit_width Input 8 Unused legacy signal.
cv_vid_in_vid_total_sample_width Input 16 Indicates the total (active + blanking) width of the raster
cv_vid_in_vid_total_line_count Input 16 Indicates the total (active + blanking) height of the raster
cv_vid_in_vid_hdmi_duplication Input 4 Unused legacy signal.
cv_vid_in_sof Output 1 Unused legacy signal.
cv_vid_in_sof_locked Output 1 Unused legacy signal.
cv_vid_in_refclk_div Output 1 Unused legacy signal.
cv_vid_in_clipping Output 1 Unused legacy signal.
cv_vid_in_padding Output 1 Unused legacy signal.
cv_vid_in_overflow Output 1 Unused legacy signal.
Table 186.  Clocked Video Output Streaming Video InterfaceThis interface is only available if you select CVO for CV Bus Style.
 
Port Name Direction Width Description
cv_vid_in_vid_clk Output 1 Pixel synchronous clock.
cv_vid_in_vid_h Input Pixels in parallel When 1, the video is in a horizontal blanking.
cv_vid_in_vid_v Input Pixels in parallel When 1, the video is in a vertical blanking.
cv_vid_in_vid_h_sync Input Pixels in parallel When 1, the video is in a horizontal synchronization period.
cv_vid_in_vid_v_sync Input Pixels in parallel When 1, the video is in a vertical synchronization period.
cv_vid_in_vid_f Input Pixels in parallel When 1, the video is interlaced and in field 1. When 0, the video is either progressive or interlaced and in field 0.
cv_vid_in_vid_data Input 27 Pixel data.
cv_vid_in_vid_datavalid Input Pixels in parallel When 1, the input is valid.
cv_vid_in_vid_underflow Input 1 Unused legacy signal.
cv_vid_in_vid_mode_change Input 1 Unused legacy signal.
cv_vid_in_vid_vcoclk_div Input 1 Unused legacy signal.
cv_vid_in_vid_sof_locked Input 1 Unused legacy signal.
cv_vid_in_vid_sof Input 1 Unused legacy signal.
cv_vid_in_vid_std Input 6 Unused legacy signal.
23

The equation gives all tdata widths in these interfaces:

max (floor(((bits per color sample x number of color planes + 1) x pixels in parallel) + 7) / 8) x 8, 16)

24

The equation gives all tuser widths in these interfaces:

N = ceil (tdata width / 8)

25

The equation gives the data width:

width = (bits per color sample X number of color planes X pixels in parallel)

26

The equation gives the data width:

width = (bits per color sample X number of color planes X pixels in parallel)

27

The equation gives the data width:

width = (bits per color sample X number of color planes X pixels in parallel)