Video and Vision Processing Suite Intel® FPGA IP User Guide
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Ixiasoft
Visible to Intel only — GUID: jwb1662566078973
Ixiasoft
29.3.1. Stream Cleaner IP Interfaces
Name | Direction | Width | Description |
---|---|---|---|
Clocks and resets | |||
main_clock_clk | Input | 1 | AXI4-S processing clock. |
main_reset_rst | Input | 1 | AXI4-S processing reset. |
Intel FPGA streaming video interfaces | |||
axi4s_vid_in_tdata | Input | 76 | AXI4-S data in. |
axi4s_vid_in_tvalid | Input | 1 | AXI4-S data valid. |
axi4s_vid_in_tuser[0] | Input | 1 | AXI4-S start of video frame. |
axi4s_vid_in_tuser[1] | Input | 1 | AXI4-S control or data packet. |
axi4s_vid_in_tuser[N-1:2] | Input | 77 | Unused. |
axi4s_vid_in_tlast | Input | 1 | AXI4-S end of packet. |
axi4s_vid_in_tready | Output | 1 | AXI4-S data ready. |
axi4s_vid_out_tdata | Output | 76 | AXI4-S data in. |
axi4s_vid_out_tvalid | Output | 1 | AXI4-S data valid. |
axi4s_vid_out_tuser[0] | Output | 1 | AXI4-S start of video frame. |
axi4s_vid_out_tuser[1] | Output | 1 | AXI4-S control or data packet. |
axi4s_vid_out_tuser[N-1:2] | Output | 77 | Unused. |
axi4s_vid_out_tlast | Output | 1 | AXI4-S end of packet. |
axi4s_vid_out_tready | Input | 1 | AXI4-S data ready |
The equation gives all tdata widths sizes in these interfaces:
max (floor(((bits per color sample x number of color planes x pixels in parallel)+ 7) / 8) x 8, 16)
This equation gives all tuser widths sizes in these interfaces: N = ceil (tdata width/ 8)