Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 9/30/2022

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Generic Crosspoint Intel® FPGA IP 23. Genlock Signal Router Intel® FPGA IP 24. Guard Bands Intel® FPGA IP 25. Interlacer Intel® FPGA IP 26. Mixer Intel® FPGA IP 27. Pixels in Parallel Converter Intel® FPGA IP 28. Scaler Intel® FPGA IP 29. Stream Cleaner Intel® FPGA IP 30. Switch Intel® FPGA IP 31. Tone Mapping Operator Intel® FPGA IP 32. Test Pattern Generator Intel® FPGA IP 33. Video Frame Buffer Intel® FPGA IP 34. Video Streaming FIFO Intel® FPGA IP 35. Video Timing Generator Intel® FPGA IP 36. Warp Intel® FPGA IP 37. Design Security 38. Document Revision History for Video and Vision Processing Suite User Guide

35.3. Video Timing Generator IP Functional Description

The IP comprises a simple but powerful counter and comparator architecture. Two counters track the real-time horizontal and vertical position of a pixel within the full-raster interface. Multiple software programmable comparators generate timing pulses for the f, v, and h signals.
Figure 84. Timing Generator high-level block diagram.

This processor decoder and register map provide a simple interface to the processor bus. The IP shows all run-time parameters for the video timing through the register map. All run-time parameters default to values provided at build-time.

These counters and logic contain a horizontal pixel counter and vertical line counter. The submodule produces the video timing signals f, v, and h as specified by the processor registers. The processor specifies additional programmable “pulses” to aid other modules in the system. For example, a programmable pulse can trigger the preload on the SDRAM controller.

This formatter takes the f, v, and h signals and forms a full-raster bus, or an Intel clocked video bus. You select the type of bus at build time.

Output Pixels

The output timing bus contains space for pixel data. The value of the pixel data can be set by the processor at run time but initially defaults to the value defined at build time.

The IP has a build-time option to include or exclude the tReady signal for the full-raster interface. However, the IP does not use this signal. The IP includes it only to allow connection to a full-raster bus that includes this signal. If the tReady signal is deasserted, the Video Timing Generator IP continues to produce data.


Figure 85. Timing for a Progressive Video ImageThe processor registers can configure the timing signals to generate sync or blank timing for a progressive image
Figure 86. Timing for an Interlaced ImageThe figure shows the processor registers can configure the timing signals to generate sync or blank timing for an interlaced image.

Clock Domains

The Timing Generator produces output on the transmit clock for the connectivity IP.

The processor interface operates on the processor clock domain. Drive the processor interface from a known stable clock, such as a dedicated processor clock. Do not drive connectivity IP from the transmit clock as it can be unstable. For example when standards change, which can potentially corrupt the processor interface.