Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 9/30/2022

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Generic Crosspoint Intel® FPGA IP 23. Genlock Signal Router Intel® FPGA IP 24. Guard Bands Intel® FPGA IP 25. Interlacer Intel® FPGA IP 26. Mixer Intel® FPGA IP 27. Pixels in Parallel Converter Intel® FPGA IP 28. Scaler Intel® FPGA IP 29. Stream Cleaner Intel® FPGA IP 30. Switch Intel® FPGA IP 31. Tone Mapping Operator Intel® FPGA IP 32. Test Pattern Generator Intel® FPGA IP 33. Video Frame Buffer Intel® FPGA IP 34. Video Streaming FIFO Intel® FPGA IP 35. Video Timing Generator Intel® FPGA IP 36. Warp Intel® FPGA IP 37. Design Security 38. Document Revision History for Video and Vision Processing Suite User Guide

30.3.1. Switch IP Latency

The switch IP latency depends on the complexity of the switch made, the configuration of the switch, the timing of the switch command, the timing on the inputs, and any backpressure experienced on the outputs.

The minimum switching latency (Lswitch) is the number of clock cycles from the submitting of a new switch configuration via a write to the COMMIT register, to the start of the first image information packet (full variants) or first line (lite variants) produced at the configured outputs.

Lswitch = Tremaining + 8 + (C ? 6 : 3)*I + 8*O


  • Tremaining = the number of cycles from the write to COMMIT to the end-of-field packet of the current input field (for full variants) or to the TLAST of the current line (lite variants) or to the next TUSER[0] (lite variants with All inputs are uninterrupted on).
  • I = The number of inputs whose state is changing (either consume, enable, disable or destination)
  • O = The number of outputs whose state is changing (either enable, disable, or source)
  • C is 1 with Autoconsume inputs on.

This equation holds in the absence of backpressure and in a fully synchronized system with all switch inputs receiving fields of the same size at the same time, and common host and main clocks.

Latency in a real system is dominated by the timing of the input fields and Lswitch usually only represents a very small percentage of overall switching time.

The fastest switching configurations are lite variants with All inputs are uninterrupted off, as changes occur at line endings, not field endings.