Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 9/30/2022
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Generic Crosspoint Intel® FPGA IP 23. Genlock Signal Router Intel® FPGA IP 24. Guard Bands Intel® FPGA IP 25. Interlacer Intel® FPGA IP 26. Mixer Intel® FPGA IP 27. Pixels in Parallel Converter Intel® FPGA IP 28. Scaler Intel® FPGA IP 29. Stream Cleaner Intel® FPGA IP 30. Switch Intel® FPGA IP 31. Tone Mapping Operator Intel® FPGA IP 32. Test Pattern Generator Intel® FPGA IP 33. Video Frame Buffer Intel® FPGA IP 34. Video Streaming FIFO Intel® FPGA IP 35. Video Timing Generator Intel® FPGA IP 36. Warp Intel® FPGA IP 37. Design Security 38. Document Revision History for Video and Vision Processing Suite User Guide

18.5. FIR Filter Registers

Each register is either read-only (RO) or read-write (RW).
Table 274.  FIR Filter RegistersIn the software API the register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE or INTEL_VVP_FIR as appropriate and with an optional REG suffix
Address Register Access Description
Lite 45 Full
Status register
0x0050 STATUS RO RO

Read this register for information about the FIR IP status

  • [0]: Scheduler running
  • [1]: Pending writes
  • [2]: Algorithmic component running.
Control and debug registers

For more information, refer to Control Packets

0x0048 IMG_INFO_WIDTH RW NA For lite designs, the expected width of the incoming video fields.
0x0049 IMG_INFO_HEIGHT RW NA For lite designs, the expected height of the incoming video fields.

0x0080

to 0x0080 + 4*(Number of coefficients-1)

COEFFICIENTS RW NA For run-time editable coefficient, the coefficients that the FIR IP uses.
45

When you turn on lite mode, registers are RW only if you turn on Debug features, otherwise they are WO. For full, turn off lite mode.