Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 9/30/2022
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Generic Crosspoint Intel® FPGA IP 23. Genlock Signal Router Intel® FPGA IP 24. Guard Bands Intel® FPGA IP 25. Interlacer Intel® FPGA IP 26. Mixer Intel® FPGA IP 27. Pixels in Parallel Converter Intel® FPGA IP 28. Scaler Intel® FPGA IP 29. Stream Cleaner Intel® FPGA IP 30. Switch Intel® FPGA IP 31. Tone Mapping Operator Intel® FPGA IP 32. Test Pattern Generator Intel® FPGA IP 33. Video Frame Buffer Intel® FPGA IP 34. Video Streaming FIFO Intel® FPGA IP 35. Video Timing Generator Intel® FPGA IP 36. Warp Intel® FPGA IP 37. Design Security 38. Document Revision History for Video and Vision Processing Suite User Guide

13.4. Clocked Video Input IP Interfaces

Table 141.  Clocked Video Input IP Interfaces
Name Direction Width Description
Clocks and Resets
vid_in_clk In 1 Input video clock
vid_in_reset In 1 Input video reset
vid_out_clk In 1 Output video clock
vid_out_reset In 1 Output video reset
cpu_clock In 1 Control interface clock
cpu_reset In 1 Control interface reset
Control Interfaces
av_mm_control_agent_address In 7 Avalon memory-mapped agent address
av_mm_control_agent_write In 1 Avalon memory-mapped agent write
av_mm_control_agent_writedata In 32 Avalon memory-mapped agent write data
av_mm_control_agent_byteenable In 4 Avalon memory-mapped agent byte enable
av_mm_control_agent_read In 1 Avalon memory-mapped agent read
av_mm_control_agent_readdata Out 32 Avalon memory-mapped agent read data
av_mm_control_agent_readdatavalid Out 1 Avalon memory-mapped agent read
av_mm_control_agent_waitrequest Out 1 Avalon memory-mapped agent wait request
Intel FPGA streaming video interfaces
axi4s_fr_vid_in_tdata In AXI4-S data in
axi4s_fr_vid_in_tvalid In 1 AXI4-S data valid
axi4s_fr_vid_in_tuser[0] In 1 AXI4-S start of video frame
axi4s_fr_vid_in_tuser[N-1:1] In Unused
axi4s_fr_vid_in_tlast In 1 AXI4-S end of packet
axi4s_fr_vid_in_tready Out 1 AXI4-S data ready
axi4s_vid_out_tdata Out AXI4-S data out
axi4s_vid_out_tvalid Out 1 AXI4-S data valid
axi4s_vid_out_tuser[0] Out 1 AXI4-S start of video frame
axi4s_vid_out_tuser[1] Out 1 Field flag for interlaced formats
axi4s_vid_out_tuser[N-1:2] Out 20 Unused
axi4s_vid_out_tlast Out 1 AXI4-S end of packet
axi4s_vid_out_tready In 1 AXI4-S data ready
External Conduits
Sof_locked Out 1 Start of frame locked signal. When asserted, the start of frame signal is valid and you can use it.
Field_flag Out 1 Field flag for interlaced formats
Sof_pulse Out 1 A single pulse indicating the start of a new frame
Sof_tgl Out 1 A signal that toggles at the start of a new frame
Video_overflow Out 1 A signal to indicate output FIFO buffer overflow
External_video_locked In 1 Assert this signal when a stable video stream is available on the input. Deassert this signal when the video stream is removed.
Status_update_interrupt Out 1 Interrupt signal
19

The equation gives the TDATA width for these interfaces for full-raster variants:

max (floor(((bits per color sample x (number of color planes + 1) x pixels in parallel) + 7) / 8) x 8, 16)

20 This equation gives the TUSER width N for these interfaces: ceil (tdata width / 8)
21

The equation gives the TDATA width for these interfaces for full or lite variants:

max (floor(((bits per color sample x number of color planes x pixels in parallel) + 7) / 8) x 8, 16)