Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 9/30/2022

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Generic Crosspoint Intel® FPGA IP 23. Genlock Signal Router Intel® FPGA IP 24. Guard Bands Intel® FPGA IP 25. Interlacer Intel® FPGA IP 26. Mixer Intel® FPGA IP 27. Pixels in Parallel Converter Intel® FPGA IP 28. Scaler Intel® FPGA IP 29. Stream Cleaner Intel® FPGA IP 30. Switch Intel® FPGA IP 31. Tone Mapping Operator Intel® FPGA IP 32. Test Pattern Generator Intel® FPGA IP 33. Video Frame Buffer Intel® FPGA IP 34. Video Streaming FIFO Intel® FPGA IP 35. Video Timing Generator Intel® FPGA IP 36. Warp Intel® FPGA IP 37. Design Security 38. Document Revision History for Video and Vision Processing Suite User Guide

15.1. About the Clocked Video Output IP

The Clocked Video Output Intel FPGA IP merges the pixel data from an AXI4-S lite or AXI4-S full video bus with the real-time video signals from a reference AXI4-S full-raster stream. The output is an AXI4-S full-raster bus that you can connect directly to the Intel Interconnect IP.

Another IP can provide the reference AXI4-S full-raster stream or an embedded Video Timing Generator Intel FPGA IP can generate the reference stream.

Second Input Fall Back

The IP provides an optional second AXI4-S Video Streaming input. If the primary input stream fails, the IP automatically changes to use the second input. If the second input also fails, or is not used, the IP produces black. You can configure the exact pixel value for black at build time and via the processor interface at runtime.

By default, when the primary video input relocks to the timing reference the IP automatically changes back to the primary video input at the start of the next frame. However, you can change the default behavior via the processor interface. Using the processor interface, you can manually control when the IP changes from the test pattern input back to the video input. You can force the IP to select either the main video input, the test pattern input, or black.

Pixels in Parallel Support

The IP supports any number of pixels in parallel from 1 to 8. The raster dimensions have no restrictions on the number of pixels in parallel. The raster width does not have to be an integer multiple of pixels in parallel.

The pixel input stage contains a barrel shift to align the AXI4-S lite or AXI4-S full streams with the AXI4-S full-raster stream.