Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 9/30/2022

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Generic Crosspoint Intel® FPGA IP 23. Genlock Signal Router Intel® FPGA IP 24. Guard Bands Intel® FPGA IP 25. Interlacer Intel® FPGA IP 26. Mixer Intel® FPGA IP 27. Pixels in Parallel Converter Intel® FPGA IP 28. Scaler Intel® FPGA IP 29. Stream Cleaner Intel® FPGA IP 30. Switch Intel® FPGA IP 31. Tone Mapping Operator Intel® FPGA IP 32. Test Pattern Generator Intel® FPGA IP 33. Video Frame Buffer Intel® FPGA IP 34. Video Streaming FIFO Intel® FPGA IP 35. Video Timing Generator Intel® FPGA IP 36. Warp Intel® FPGA IP 37. Design Security 38. Document Revision History for Video and Vision Processing Suite User Guide

9.1. About the AXI-Stream Broadcaster IP

The IP broadcasts an input video streaming to multiple output video streaming interfaces. Both video input and output interfaces work on the same clock domain. The IP comprises the main AXI4-Stream broadcast logic and synchronous streaming FIFO buffers.

The broadcast logic replicates the video streaming input bus to N outputs. You specify N at build time. The IP offers full, lite, and full-raster variants of Intel FPGA streaming video. For more information, refer to the Intel FPGA Streaming Video Protocol Specification.

To process TREADY backpressure on the output interfaces, each output has either a FIFO buffer of configurable depth, or a shim, which is equivalent to a 1-depth FIFO buffer. If an output deasserts its TREADY, its FIFO buffer continues to accept input until it is full. If any one of the output FIFO buffers is full and you turn on Global stall, the broadcaster stalls the input by deasserting its TREADY. The IP stops new input from filling any of the FIFO buffers until all the FIFO buffers are ready to accept new data. If you turn off Global stall option, the broadcaster input never stalls but the FIFO buffers drop new input when they are full. In either case, each output always asserts TVALID when data is present in its FIFO buffer.

Typically, you use full-raster variants for real-time video. The input and output TREADY signals are entirely optional. Disabling TREADY on any interface removes the signal and stops any backpressure on that interface. For outputs, this action replaces the FIFO buffer with a simple register stage. If you do not turn on TREADY on any of the outputs, global stall has no effect and the IP removes the option.

With these different backpressure options available, you consider the system design and determine what amount of backpressure is acceptable on each interface. For example, a processing pipeline operating on non-real-time video streams might want the global stall option. However, in a system where the broadcaster is dealing with real-time video, stalling the input might be unacceptable. Output FIFO buffers must be large enough so that no pushback reaches the broadcaster.