Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 9/30/2022
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Generic Crosspoint Intel® FPGA IP 23. Genlock Signal Router Intel® FPGA IP 24. Guard Bands Intel® FPGA IP 25. Interlacer Intel® FPGA IP 26. Mixer Intel® FPGA IP 27. Pixels in Parallel Converter Intel® FPGA IP 28. Scaler Intel® FPGA IP 29. Stream Cleaner Intel® FPGA IP 30. Switch Intel® FPGA IP 31. Tone Mapping Operator Intel® FPGA IP 32. Test Pattern Generator Intel® FPGA IP 33. Video Frame Buffer Intel® FPGA IP 34. Video Streaming FIFO Intel® FPGA IP 35. Video Timing Generator Intel® FPGA IP 36. Warp Intel® FPGA IP 37. Design Security 38. Document Revision History for Video and Vision Processing Suite User Guide

21.3.1. Full-Raster to Streaming Converter Interfaces

The IP has two functional video interfaces, two clock domains, and two resets. The Intel FPGA streaming video protocol and the full-raster variant are standard interfaces to connect components that exchange video data.

All two input clocks are asynchronous from each other. Internally, the IP includes clock domain crossing circuits for both single bit and data bus signal cases, which safely allows data exchange between any of the two asynchronous clock domains. The IP also includes an embedded entity .sdc file, which provides all the necessary information to the Timing Analyzer. For system integration, when you instantiate the IP in a design, the only constraints required are:

  • Clock frequency constraints for the input video clock (vid_in_clock_clk)
  • Clock frequency constraints for the output video clock (vid_out_clock_clk)
Table 323.  Full-Raster to Streaming Converter input and output video interfaces
Name Direction Width Description
Clocks and resets
vid_in_clock_clk In 1 Input AXI4-S full-raster processing clock.
vid_in_reset_reset In 1 Input AXI4-S full-raster processing reset.
vid_out_clock_clk In 1

Output AXI4-S active-video

processing clock.

vid_out_reset_reset In 1

Output AXI4-S

processing reset.

Intel FPGA streaming video interfaces
axi4s_fr_vid_in_tdata in 55 56 AXI4-S data in.
axi4s_fr_vid_in_tvalid in 1 AXI4-S data valid.
axi4s_fr_vid_in_tuser[pixels in parallel-1:0] in 1 AXI4-S start of video frame.
axi4s_fr_vid_in_tuser[N-1:pixels in parallel] in 57 Unused.
axi4s_fr_vid_in_tlast in 1 AXI4-S end of packet .
axi4s_fr_vid_in_tready out 1 Optional AXI4-S data ready.
axi4s_vid_out_tdata out 58 59 AXI4-S data in.
axi4s_vid_out_tvalid out 1 AXI4-S data valid.
axi4s_vid_out_tuser[0] out 1 AXI4-S start of video frame.
axi4s_vid_out_tuser[N-1:1] out 60 Unused.
axi4s_vid_out_tlast out 1 AXI4-S end of packet.
axi4s_vid_out_tready in 1 AXI4-S data ready.
55

The equation gives all full-raster tdata width sizes in these interfaces:

max (floor((( bits per color sample x (number of color planes+1) x pixels in parallel) + 7) / 8) x 8, 16)

56

The equation gives all tdata width sizes in these interfaces:

max (floor((( bits per color sample x number of color planes x pixels in parallel) + 7) / 8) x 8, 16)

57

The equation gives all tuser width sizes in these interfaces:

N = ceil (tdata width / 8)

58

The equation gives all full-raster tdata width sizes in these interfaces:

max (floor((( bits per color sample x (number of color planes+1) x pixels in parallel) + 7) / 8) x 8, 16)

59

The equation gives all tdata width sizes in these interfaces:

max (floor((( bits per color sample x number of color planes x pixels in parallel) + 7) / 8) x 8, 16)

60

The equation gives all tuser width sizes in these interfaces:

N = ceil (tdata width / 8)